- Ultra-Low-Latency: less than one msec latency for most widely used formats
- High performance: 2.5 cycles per pixel; Full-HD capable
- ISO/IEC 14496-10/ITU-T H.264, Constraint Baseline Profile specification
- I and P slices (Intra-only version also available)
- Multiple slices per frame
- Multiple reference frames
- Multiple sequence parameter sets (SPS)
- Multiple picture parameter sets (PPS)
- In-loop deblocking filter
- CAVLC entropy decoding
- Real time performance up to level 4.1
- Progressive, 4:2:0 YCbCr with 8 bits per color sample
- From QCIF (176x144), to 2048x2048 resolutions
- No decoded frame buffering
- Decoded pixels are streamed-out output with less than one macro-block lines of latency
- Less than 1 msec for almost all widely used video formats
Ease of Integration
- Zero CPU overhead, stand-alone operation
AMBA® AXI external memory interface is independent of memory type and tolerant to latencies
- Streaming interfaces for bit-stream and pixel data, with flow control; easily bridged to AMBA® AXI Streaming
- Error catching and reporting capability
- Reports video format and enables cropping
- Optional Block to Raster
- Silicon proven
- Verified with Fraunhofer H.264 Compliance Test Streams suite
Call or click.
- H264-E-BPS Low-Power AVC/H.264 Baseline Profile Encoder Core
- H264-E-MPS Low-Power AVC/H.264 Main Profile Encoder Core
- H264-E-HIS Intra-Only High Profile Encoder Core
- H264-E-BPF Ultra-Fast AVC/H.264 Baseline Profile Encoder Core
- H264-E-MPF Ultra-Fast AVC/H.264 Main Profile Encoder Core
- H264-LD-BP Low-Power AVC/H.264 Baseline Profile Decoder Core
- H265-MP-D HEVC/H.265 Main Profile Video Decoder
- H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem
- H264OIP-HDD H.264 Video Over IP – HD Decoder Subsystem
- Choosing the Right IP Cores for Low-Latency Video Streaming
- IoT Phase 2: Design Matters
- White Paper: Understanding—and Reducing—Latency in Video Compression Systems
See more H264 blog posts >>>
H264-D-BPLow-Latency AVC/H.264 Baseline Profile Decoder Core
The H264-D-BP IP core is a video decoder complying with the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It implements a hardware decoder with very low latency and high throughput that is suitable for live streaming and other delay-sensitive applications up to full HD resolution.
The decoder adds just one macroblock line of latency, which means a negligible real-world latency under one msec for most widely used video formats, including HD/720p and Full-HD/1080p video.
The H264-D-BP is designed for straightforward, trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds with no assistance or input from the host processor. The decoder’s memory interface—used to store reconstructed video data—is independent from the external memory type and memory controller, and is tolerant to large latencies. Optionally, the core can be reduced to support only Intra-coded streams, in which case the required external memory is just 128kB and can be implemented on-chip. The decoder reports decompressed video parameters, detects and reports bit stream errors to the system, and simplifies video cropping at its output. The core is optionally delivered with a raster-to-block converter, and wrappers for AMBA® AHB, AXI, or AXI-Streaming buses are available.
See representative implementation results (each in a new pop-up window):
The H264-D-BP is suitable for broadcasting, surveillance, industrial, defense, and medical live-streaming applications with low-latency requirements and resolutions up to Full-HD.
The core is available in source-code VHDL or as a targeted netlist, and its deliverables include everything required for successful implementation:
- Source-code VHDL (ASICs) or as a targeted netlist (FPGAs)
- Sophisticated self-checking Testbench
- Synthesis scripts
- Simulation script, vectors and expected results
- Software Bit-Accurate Model
- Comprehensive user documentation
Silicon Resources Utilization
The H264-D-BP synthesizes to less than 500k gates and requires 532 kbits of internal memory. When configured to support only Intra-coded streams, the core synthesizes to about 400k gates, and requires only 128kB of external memory.
Potential customers can readily evaluate the video decoder’s low latency characteristics by using the Video over IP reference design with compressed stream captured over Ethernet, and decoded video driving an HDMI interface.
H.264 Cores Family
The H264-D-BP is one member of the family of H.264 cores that CAST offers. The following tables summarize the family members and highlight their basic features.
Low Power Encoders
2 or 1
|2 or 1|
|ASIC (16nm) Performance||UHD/4k@30||UHD/4k@30||1080p60||1080p60||UHD/4k@60||UHD/4k@60|
|Silicon Resources 1||Very Small||Small||Small||Moderate||Moderate–High||Moderate–High|
|Main||High 10 Intra||Constrained
|Slices Types||IDR||IDR, P||IDR, P||IDR||IDR, P||IDR, P|
|Bits per sample||8||8||8||8, 10||8||8|
|Multiple video channels||Optional||Optional||Optional||Optional||Optional|
|CAVLC / CABAC||/||/||/||/||/||/|
|CBR and VBR|
- Very Small <100K Gates, Small <200K Gates, Moderate <500K Gates, and High >500K Gates.
|Profile||Constrained Baseline||Constrained Baseline|
|Profile Compatibility||Full||Limited to stream from the H264-E-BPS/BPF, amd BIS cores|
|Additional Features||Interlaced with Main Profile Syntax|
- Very Small <100k Gates, Moderate <500K Gates