Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Constrained Baseline Profile AVC/H.264 decoder
  • Ultra-Low-Latency: less than one msec latency for most widely used formats
  • High performance: 2.5 cycles per pixel; Full-HD capable

Support

  • ISO/IEC 14496-10/ITU-T H.264, Constraint Baseline Profile specification
    • I and P slices
    • Multiple slices per frame
    • Multiple reference frames
    • Multiple sequence parameter sets (SPS)
    • Multiple picture parameter sets (PPS)
    • In-loop deblocking filter
    • CAVLC entropy decoding
  • Real time performance up to level 4.1

Video Formats

  • Progressive, 4:2:0 YCbCr with 8 bits per color sample
  • From QCIF (176x144), to 2048x2048 resolutions

Low Latency

  • No decoded frame buffering
  • Decoded pixels are streamed-out output with less than one macro-block lines of latency
  • Less than 1 msec for almost all widely used video formats

Ease of Integration

  • Zero CPU overhead, stand-alone operation
  • AMBA® AXI external memory interface: uses separate clock, is independent of memory type and tolerant to latencies
  • Streaming interfaces for bit-stream and pixel data, with flow control; easily bridged to AMBA® AXI Streaming
  • Error catching and reporting capability
  • Reports video format and enables cropping
  • Optional Block to Raster

Maturity

  • Silicon proven
  • Verified with Fraunhofer H.264 Compliance Test Streams suite

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Compare
Versions

Encoders

  • H264-E-BPS Low-Power AVC/H.264 Baseline Profile Encoder Core
  • H264-E-MPS Low-Power AVC/H.264 Main Profile Encoder Core
  • H264-E-HIS Intra-Only High Profile Encoder Core
  • H264-E-BPF Ultra-Fast AVC/H.264 Baseline Profile Encoder Core
  • H264-E-MPF Ultra-Fast AVC/H.264 Main Profile Encoder Core

Decoders

  • H264-LD-BP Low-Power AVC/H.264 Baseline Profile Decoder Core
  • H265-MP-D HEVC/H.265 Main Profile Video Decoder

Subsystems

  • H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem
  • H264OIP-HDD H.264 Video Over IP – HD Decoder Subsystem

News Releases

Blog Posts

See more H264 blog posts >>>

H264-D-BPLow-Latency AVC/H.264 Baseline Profile Decoder Core

The H264-D-BP IP core is a video decoder complying with the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It implements a hardware decoder with very low latency and high throughput that is suitable for live streaming and other delay-sensitive applications up to full HD resolution.

The decoder adds just one macroblock line of latency, which means a negligible real-world latency under one msec for most widely used video formats, including HD/720p and Full-HD/1080p video.

The H264-D-BP is designed for straightforward, trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds with no assistance or input from the host processor. The decoder’s memory interface—used to store reconstructed video data—is extremely flexible: it operates on a separate clock domain, is independent from the external memory type and memory controller, and is tolerant to large latencies. The decoder reports decompressed video parameters, detects and reports bit stream errors to the system, and simplifies video cropping at its output. The core is optionally delivered with a raster-to-block converter, and wrappers for AMBA® AHB, AXI, or AXI-Streaming buses are available.

See representative implementation results (each in a new pop-up window):

PCIe core ASIC numbers Altera numbers Xilinx numbers

Applications

The H264-D-BP is suitable for broadcasting, surveillance, industrial, defense, and medical live-streaming applications with low-latency requirements and resolutions up to Full-HD.

Block Diagram

h264-d-bp Low-Latency AVC/H.264 Baseline Profile Decoder Block Diagram

Deliverables

The core is available in source-code VHDL or as a targeted netlist, and its deliverables include everything required for successful implementation:

Silicon Resources Utilization

The H264-D-BP synthesizes to about 500k gates and requires 530 kbits of internal memory.

Evaluation

Potential customers can readily evaluate the video decoder’s low latency characteristics by using the Video over IP reference design with compressed stream captured over Ethernet, and decoded video driving an HDMI interface.

H.264 Cores Family

The H264-D-BP is one member of the family of H.264 cores that CAST offers. The following tables summarize the family members and highlight their basic features.

H.264
Encoder
Cores

Low Power Encoders

Fast Encoder

Ultra-Fast Encoders

H264-E-BIS
Low-Power Intra-Only
Baseline Profile Enc

H264-E-BPS
Low-Power
Baseline Profile Encoder

H264-E-MPS
Low-Power
Main Profile Encoder

H264-E-HIS
Intra-Only
High Profile Encoder

H264-E-BPF
Ultra-Fast
Baseline Profile Encoder

H264-E-MPF
Ultra-Fast,
Main Profile Encoder

Throughput (cycles/pixel) 4 4 4 2.5

2 or 1

2 or 1
ASIC (16nm) Performance UHD/4k@30 UHD/4k@30 1080p60 1080p60 UHD/4k@60 UHD/4k@60
Silicon Resources 1 Very Small Small Small Moderate Moderate–High Moderate–High
Profile Constrained
Baseline
Constrained
Baseline
Main High 10 Intra Constrained
Baseline
Main
Slices Types IDR IDR, P IDR, P IDR IDR, P IDR, P
Chroma Formats 4:2:0 4:2:0 4:2:0 4:2:0 4:2:0 4:2:0
Bits per sample 8 8 8 8, 10 8 8
Progressive/Interlaced included/ included included/ included included/ not supported included/ not supported included/ included included/ not supported
Multiple video channels Optional Optional Optional not supported Optional Optional
CAVLC / CABAC included/ not supported included/ not supported not supported/ included included/ not supported included/ not supported not supported/ included
CBR and VBR included included included not supported included included
Intra-Refresh N/A included included N/A included included
Multiple Slices included included included not supported included included

Notes:

  1. Very Small <100K Gates, Small <200K Gates, Moderate <500K Gates, and High >500K Gates.

 

H.264
Decoder Cores

H264-D-BP
Low Latency Baseline Profile Decoder

H264-LD-BP
Low Power Baseline Profile Decoder

Profile Constrained Baseline Constrained Baseline
Profile Compatibility Full Limited to stream from the H264-E-BPS/BPF, amd BIS cores
Additional Features not supported Interlaced with Main Profile Syntax
Throughput (cycles/pixel)

2.5

4

Silicon Resources1 Moderate Small

Notes:

  1. Very Small <100k Gates, Moderate <500K Gates

 

 

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