H264-D-BP Core — ASIC Implementation Results

The H264-D-BP can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample implementation data. Note that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology.


Logic Area


Logic Area







tsmc16-sc7-svt 85,390
494,155 532 1,000 400
tsmc28hpm-sc9-c35-svt-ss 257,570
529,979 532 1,000 400
tsmc40g-sc9-rvt 257,570 645,329 532 800 320

When configured to support only Intra-coded streams, the core synthesizes to about 400k gates, and requires only 128kB of external memory.


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