H.264 IP Core H264-BP-E H.264/AVC HD & ED Video Encoder Core

On this page: Description | Applications | Features | Block Diagram | Functional Description | Support | Deliverables | Evaluation | Related Cores

This H.264-BP-E IP core implements a video encoder compatible to the Baseline profile of the H.264 standard, also known as MPEG-4 Part 10.

The H.264-BP-E core can encode at Full HD (1080p@30) or higher rates, even in low-cost FPGAs. Employing innovative techniques and algorithms, it provides quality beyond typical H264 Baseline Profile encoders. The core can perform constant bit rate (CBR) compression that produces the highest possible quality while fitting the output to a specified bit rate, or constant-Qp, variable bit rate (VBR) compression to achieve a uniform quality level among frames.

The H.264-BP-E core can be configured to operate on Intra-Only mode, offering compression efficiency superior than this of JPEG and competitive to this of JPEG2000. Under this configuration the requirements for an external memory can be eliminated, the core’s size is cut to half, and the output stream remains H264 compliant. With Intra-only compression each frame is coded independently, allowing for smaller processing delays, easier video editing, and enhanced error resilience.

The core is designed for ease and trouble-free integration. It can automatically convert incoming frames to the macroblock format required by the H.264 standard, and it outputs the standard H.264 Annex B NAL byte stream. Also, the employed CBR algorithm provides user-controlled granularity, and the CBR output stream is HRD compliant respecting decoder’s buffering requirements.  Furthermore, the core operates independently from a host processor and is run-time programmable for user control over compression parameters and bit rate options. Finally, a flexible external memory interface makes the core independent of memory type—supporting SRAM, SDRAM, or DDRAM—and more tolerant to the large delays and latencies typically present on a shared bus architecture.

The core is designed for reuse and reliability, and has been rigorously verified and FPGA proven. System integration is facilitated by the core’s complete verification environment, with additional aids for system-on-chip simulation available such as a software bit-accurate model (BAM) and a complete hardware/software reference design system.

See representative implementation results (each in a new pop-up window):

Applications

The H264-BP-E core efficiently handles extended definition (ED) through high definition (HD) video, and is suitable for a range of applications including surveillance and monitoring, video conferencing, and streaming video on demand.

Features

H.264 Video Encoding

• Fully compliant to the ISO/IEC 14496-10/ITU-T H.264 baseline specification (MPEG-4 Part 10, Advanced Video Coding)
• Profile level up to 5.1
• Flexible 4:2:0 video input
• Planar scan
• Interleaved scan
• Macroblock scan
• Automatically converts video input to the macroblock format required for H.264 processing
• Produces a ITU-T H.264 Annex B compliant NAL video byte stream
• Compression efficiency from QCIF up to HD resolutions
• Programmable bit rate control
• Constant bit rate compression
• Constant Qp compression
• Single reference frame
• Advanced Inter-Prediction
• Full Search
• Quarter pel accuracy
• Variable block size
• Block skipping
• Up to 32x20 search area 
• Advanced intra prediction modes
• All four Intra 16x16 luma prediction modes
• All four Intra chroma prediction modes
• All nine Intra 4x4 luma prediction modes
• Advanced Intra prediction in Inter slices
• Multiple slices for enhanced error resilience
• Advanced mode selection for superior compression and quality
• CAVLC Encoding
• In-Loop deblocking filter
• Optional Intra-only coding

System Integration

• Processor-independent, stand-alone operation
• Independent of external memory type (DDR2/3. SDRAM, SRAM, etc.)
• Glue-less connection to Xilinx, Altera and CAST memory controllers
• Low latency
• Bit Accurate Model
• Available Reference Design System hardware/software package

Block Diagram

Functional Description

The H264-BP-E core is a hardware implementation of the H.264 baseline video compression algorithm, designed to process video with resolution up to 4k x4k pixels. It consists of a number of functional blocks, as shown in the diagram and described here.

For each block of pixels, the Intra Prediction unit generates a suitable prediction. In the case of P-frames, the Motion Estimation Unit also generates a prediction, operating with quarter-pixel accuracy. The prediction cost of each unit is estimated using Lagrange multipliers, and the best is selected for encoding.

The residual information is calculated from the difference between the current block and the prediction. Constant or variable bit rate calculations are applied. The data is then transformed and quantized to be encoded by the Entropy Coding unit.

The transformed, quantized residual is also used to reconstruct a reference frame, which will be used during the encoding of future P-frames. This is achieved by inverse quantization and transformation of the residual, which is then added back to the prediction. Finally, the reconstructed frame is filtered before being stored back in the external memory.

The core can perform macroblock skipping that is important for low data rate applications, and supports multiple slices that enhance error resilience of the compressed stream.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes:

• HDL RTL source code (ASICs) or post-synthesis netlist (FPGAs)
• Sophisticated self-checking Testbench  (Verilog versions use Verilog 2001)
• Software (C++) Bit-Accurate Model and test vector generator
• Synthesis scripts (ASIC) or place and route script (FPGAs)
• Simulation script, vectors and expected results
• Comprehensive user documentation, including detailed specifications and a system integration guide

Evaluation

The video encoder’s extremely high visual quality is best evaluated by compressing examples of an application’s actual input video. There are three ways to do this.

• Work directly with CAST’s video compression engineers,
• Use the available BAM for software simulation, or
• Use the available H264-AP H.264 Application Platform, a board and software package combining the H.264 Encoder, memory and controller, and other IP cores with software drivers and a graphical user interface for H.264 control.

Related Cores

• CMMI-H264 Multimedia Interface – adds an AHB interface to the H264-BP-E core
• H264-MP-E H.264 Main Profile Encoder Core

 

Please contact CAST Sales to discuss your specific project requirements (sales@cast-inc.com) (+1 201.391.8300).

On this page: Description | Applications | Features | Block Diagram | Functional Description | Support | Deliverables | Evaluation | Related Cores

Download PDF datasheets for more info: ASIC | Altera | Xilinx