DV IP Core DV-E DV Encoder Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | FPGA Development & Evaluation Platform | Support | Verification | Deliverables

It implements a DV video encoder in custom hardware, able to provide high quality standard definition (SD) and high definition (HD) video streams at 25Mbps, 50MBps and 100Mbps. The core supports the ISO/IEC 61834, the SMPTE 314M, and the SMPTE 370M standards, and is compatible all DV variants, including the DVCAM, DVCPRO, and DVCPRO-HD formats.

Using an advanced multi-pass quantization engine, the core provides superior image quality while maintaining the strict DV limits on bit rate. The highly flexible core supports multiple frame formats and pixel depths of 8 bits per color for SD and HD sources, as well as 10 bits per color for HD sources.

The video encoder is designed for straightforward, trouble-free SoC integration. It operates on a stand-alone basis, and requires minimal host-processor intervention for configuration, command, and errors handling. The core’s configuration and status registers are accessible via a AMBA® APB 3.0 interface. Incoming uncompressed frames are read from, and resulting compressed stream is stored to an external memory. The external memory interface is independent of memory type—supporting SRAM, SDRAM, or DDRAM—and tolerant to the large delays and latencies typically present on a shared bus architecture.

The core is designed for reuse and reliability, and has been validated for standard conformance and is multiple times production proven in high volume consumer devices. A complete ‘C’ reference driver and fully documented API facilitate system integration. An optional FPGA-based reference system using the core provides a complete development environment for evaluation and early software development.

Features

Standards Support

• ISO/IEC 61834
• SISO/IEC 61834
• SMPTE 314M / 370M
• DV, DVCAM, DVCPRO 25/50, DVPRO HD

Flexible Frame Format

• SD and HD resolution including
• SD: 524/60i, 625/50i
• HD: 1080/60i, 1080/50i, 720p/60p
• Interlaced and progressive video
• 4:2:0 and optional 4:2:2 sub-sampling
• 8 bits per color SD and HD, and 10 bits per color for HD

Easy SoC Integration

• Processor-independent, stand-alone operation
• Standard & Customizable Interfaces
• AMBA/APB 3.0 for status/control
• Generic memory controller for uncompressed frames and compressed stream
• Different interfaces available up on request
• Independent of external memory type: can use DDR2/3. SDRAM, SRAM, and others
• Tolerant to memory latency
• Includes 'C' reference driver and fully-documented API
• Available ready-to-run FPGA Development and Evaluation Platform integrates decoder core with peripherals, memory, interfaces, and essential software
• Companion image scaler core available

Efficient and Mature Design

• 175k Gates in 65nm and 461 Kbits of internal RAM
• Just 135MHz for HD encoding
• Production proven in high-volume consumer devices
• Rigorously verified and validated

Applications

The decoder is an excellent choice for a variety of applications, including:

• Broadcasting equipment
• Professional studio, ENG, and EFP cameras
• Industrial cameras
• Consumer electronics camcorder

Block Diagram

 

Implementation Results

The DV-E core was developed using best-in-class design principles and is very efficient in resource usage and clock rates. It can encode HD using a clock of 135MHz, and SD with a clock of 75MHz. The following table provides indicative implementation result.

Technology	Area	Memory	Special Features	Fmax (MHz)
TSMC 65nm	175K gates	461 Kbits	-	>200
Altera Stratix-IV	23,000 ALUTs	15 M9Ks	33 MULT	150
Xilinx Virtex-5	5,200 Slices	15 BRAM	36 DSP	150

  Please contact CAST for detailed area and timing results for any specific technology you require.

FPGA Development & Evaluation Platform

The FPGA Development & Evaluation Platform available with this core implemented in an FPGA allows quick and cost-effective evaluation and early software prototyping.

The ready-to-run platform includes a 32-bit host processor capable of running custom applications, DVI and other built-in interfaces, and a peripherals suite running a flash-based ROM monitor that loads at power-up.

The ROM monitor allows for the development and download of customer specific application code developed using GCC, enabling simultaneous hardware and software evaluation.

 

Support

The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The DV-E has been rigorously verified using random and directed testing covering corner condition across a wide variety of resolutions. Furthermore, it has been validated using external and internal compliance test suites. The results of the compliance testing are available upon request. Extensive interoperability testing has also been conducted using a wide variety of shipping decoder products. The core has been multiple times production proven.

Deliverables

The core includes everything required for successful implementation:

• HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
• Reference driver, API and video player application in C
• Sophisticated shelf-checking HDL Testbench
• Simulation script, vectors, expected results, and timing constraints simulation summary
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including a fully documented API, and functional specification.

On this page: Description | Implementation Results | Features | Applications | Block Diagram | FPGA Development & Evaluation Platform | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx