Graphics Accelerator IP Core 2D-GRAPHACC 2D Graphics Accelerator Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Descriptions | Support | Verification | Deliverables

Implements a graphics processing unit that accelerates basic two-dimensional graphics functions, including block transfers, vector drawing, and bit-block transfer (BitBLT) primitives.

Using a tile-based architecture, the core intelligently manages memory system bandwidth and is tolerant to memory latencies making it ideal for use in shared memory architectures.

The frame store is maintained in external memory and is accessed through a direct, high-speed, wide, bus memory interface. Multiple rendering buffers are supported with unique buffers supported for each source or destination image. Frame buffer formats of 32 or 16 bits per pixel are supported for all operations.

The core’s high speed AMBA 2.0 compliant AHB slave interface is ideal for display list DMA operations. It supports a wide range of applications via multiple host management mechanisms, including host polling, host interrupts, or direct DMA control to provide a continuous stream of rendering commands to the core.

The graphics accelerator core is available for ASICs or FPGAs, and includes a complete ‘C’ reference driver and fully documented API. The core has been customer-proven, and is available in an optional FPGA-based reference system that provides a complete development environment for evaluation and early software development.

See representative implementation results (each in a new pop-up window):

Features

High performance rendering to a broad range of video applications

• High Performance
• Block fill, vector draw, BitBLT, and Rotated BLT support
• Reference driver included

Easy Integration

• AMBA 2.0 AHB slave interface for high speed display list transfers
• Direct to memory interface for all pixel data
• Fully synchronous soft core

Rendering Support

• 512MB addressable range
• Image sizes up to 4K x 4K
• 32-bit or 16-bit color depth
• Programmable clip region

Block Fill and Vector Drawing

• Solid fill or edge modes
• Programmable stipple pattern

BitBLT

• Transparent BLT
• 3 Source raster operations
• Negative addressing for window moves
• Font rendering support
• Pattern BLT
• Rotated BLT of 90, 180, or 270 degrees

FPGA Development & Evaluation Platform

• Integrated 32-bit microprocessor
• Video input for real time testing
• Includes the VDINT-MA Deinterlacer, DDR-2 interface, and DVI digital display controller

Applications

The 2D-GraphAcc graphics accelerator brings high-performance 2D rendering to a broad range of applications, including GUI-driven industrial, automotive and medical systems.

Block Diagram

Functional Description

The 2D graphic accelerator core provides a high-performance suite of basic rendering functions. Controlled through an integrated command buffer, the core is capable of sustained fill rates of one pixel per clock cycle.

Each function is capable of accessing a memory-based render buffer of up to 4096 by 4096 pixels with a color depth of either 16 or 32 bits. Centralized tile buffers support a rectangular clipping region as well as color plane masking of all pixels.

The major functional units are identified in the block diagram and explained below.

BlockFill

Provides a fast and efficient method for filling rectangular regions with a solid color. Supports a solid fill mode, and an edge mode that renders only the pixels along the edge of the designated rectangle with a programmable line width.

Vector

Performs primitive line drawing using a form of the Bresenham algorithm. A wide range of line styles are supported through programmable line weights and a variable stipple pattern. A 32-bit stipple register allows for a wide range of non-solid lines. Stipple patterns support both a foreground and a background color.

Rotation Engine

Performs axis-aligned rotations. Rectangular image regions may be rotated using a programmable angle of 0, 90, 180, or 270 degrees, and the controller supports the horizontal flip and vertical flip functions.

BitBLT

A versatile function that supports multiple transfer modes using up to three source buffers and a single destination buffer. The three source buffers each support 256 raster operations as well as implementing a destination transparent BLT and destination chroma keying. Source buffers need not be in raw pixel format, but may consist of color or monochrome patterns.

Additional modes support enhanced rendering for window-based GUIs, including negative addressing for window move operations and run length encoded BLTs for fast graphical unpacking of simple images.

Color Depth

Supports color depths of both 32-bits per pixel and 16-bits per pixel. All internal compositing functions are performed at 32-bits per pixel, and source images are converted to 32-bits per pixel prior to compositing. Destination images are converted to 16-bits per pixel before being written to the destination frame buffer. The color depth of each source or destination buffer may be set independently.

Support

The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

Verification tests have been performed at both the module and system levels. The module level tests help identify the source of system level test bench failures, and are also employed when the customer modifies the HDL source and the design engineer requires feedback on the impact of those modifications.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
  
• Reference driver, and rendering demonstration application in C
  
• Sophisticated HDL self-checking Testbench
  
• Generic SRAM simulation models
  
• Synthesis (soft) or place and route (firm) script
  
• Comprehensive user documentation, including a functional specification.

 

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Descriptions | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx