H16750S Core — Intel Implementation Results

The H16750S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). H16750S reference designs have been evaluated in a variety of technologies.  The following are sample Altera results optimized for speed. Please contact CAST to get characterization data for your target configuration and technology.

Family Logic Resources Memory bits Clock Freq. (MHz)
Cyclone V 522 ALMs 1,216 140
Arria V 502 ALMs 1,216 205
Stratix V 538 ALMs 1,216 282
Arria 10 531 ALMs 1,216 342
Max 10 1,020 LEs 1,216 154

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