Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
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BA21 Low Power
BA20 PipelineZero

Peripheral Platforms
& AMBA Infrastructure

BA2x AHB Platform
BA2x AXI Platform


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These video and image compression cores and subsystems help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
J2K Platform

Lossless Image Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Lossless Data Compression
GZIP Compressor
GZIP Reference Design
GUNZIP Decompressor

Complement or replace system processors with GPUs and easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

NOR Flash Controllers
Serial/SPI NOR Flash
Parallel NOR Flash

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

AMBA Infrastructure
AMBA Infrastructure Cores
Multi-Channel DMA

Interconnect Peripherals

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Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
Hardware RTP Stack for H.264
• MPEG Transport Stream Encapsulator

Data Link Controllers

PCI — Target
32-bit multi
PCI — Master
32-bit multi
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

DES single
DES triple

  • Capable of running all existing 16450 and 16550a software
  • Fully Synchronous design. All inputs and outputs are based on rising edge of clock
  • In FIFO mode, the transmitter and receiver are each buffered with 16 byte FIFOs to reduce the number of interrupts presented to the CPU
  • Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
  • Independently controlled transmit, receive, line status and data set interrupts
  • Programmable baud generator divides any input clock by 1 to (2**16 - 1) and generates the 16 x clock
  • Modem control functions (CTSn, RTSn, DSRn, DTRn, RIn, and DCDn)
  • Fully programmable serial interface characteristics:
    • 5, 6, 7, or 8 bit characters
    • Even, odd, or no-parity bit generation and detection
    • 1, 1½, or 2 stop bit generation
    • Baud generation
  • False start bit detection
  • Complete status register
  • Internal diagnostic capabilities: loopback controls for communications link fault isolation
  • Full prioritized interrupt system controls

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PDF Datasheets

Microsemi, Altera, Lattice, Xilinx

Options for this Core

Related Products

  • H16450S Synchronous 16450 UART
  • H16750S Synchronous 16750 UART with FIFO & IrDA


H16550S Synchronous 16550 UART with FIFO Core

The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices.

The H16550S can be run in either 16450- compatible character mode or in 16550- compatible FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead.

Developed for easy reuse in FPGA or ASIC applications, the H16550S is available optimized for several technologies with competitive utilization and performance characteristics.

See representative implementation results (each in a new pop-up window):

ASIC numbers Microsemi numbers Altera numbers Lattice numbers Xilinx numbers


The H16550S core can be utilized for many communication applications including:

Symbol Diagram

H16550S UART with Synchronous CPU Interface Symbol Diagram

Block Diagram

H16550S UART with Synchronous CPU Interface Block Diagram


The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.


The core has been verified through extensive simulation and rigorous code coverage measurements.


The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:




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