H16550S Core — XILINX FPGA Results

The H16550S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data with IOBs assuming all core I/Os are routed off-chip.  Different results can be obtained by optimizing slices for area or speed. Please contact CAST to get characterization data for your target configuration and technology.

Supported Family Slices

BRAM IOBs
Fmax
(MHz)
ISE/Vivaldo Version
Spartan-3E
3S1200E-5
379 2 39 84 12.2i
Spartan-6
6SLX25-3
152 2 39 149 12.2i
Virtex-5
5VLX30-3
134 2 39 249 12.2i
Virtex-6
6VLX130T-3
135 2 39 270 12.2i
Virtex-7X
7VX330T-3
154 0 39 387 v2012.2
Artix-7
7A350T-3
160 0 39 266 v2012.2
Kintex-7
7K325T-3
177 0 39 392 v2012.2

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