H16550S Core — Intel Implementation Results

The H16550S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Supported
Family
Utilization Fmax
(MHz)
Quartus
Version
LEs Memory
Flex
EPF10K30-1
749 3 EABs 69  
Acex
EP1K30-1
749 3 EABs 69  
Apex
EP20K30-1
648 3 EABs 80  
Cyclone
EP1C20-6
547 2 M4Ks 137  
Cyclone-II
EP2C70-6
634 2 M4Ks 145 7.2
Cyclone-III
EP3C40-6
635 2 M9Ks 162 7.2
Stratix
EP1S20-5
546 2 M4Ks 142  
Stratix-II
EP2S180-3
487 1 M4K / 1 M512 216 7.2
Stratix-III
EP3SE260-4
502 1 M9K 125 7.2

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