H16550S Core — Microsemi Implementation Results

The H16550S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Family Resources Utilization Fmax
(MHz)
Throughput
(Mbps)
Sequential Combinatorial
RTAX
RTAX1000S-1
324 Cells 765 Cells 75 4.68

SmartFusion2

M2S150-STD
325 SLE 804 LUT 136 8.5

Igloo2

M2GL150-STD
325 SLE 804 LUT 136 8.5

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