H16450S Core — XILINX FPGA Results

The H16450S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data with all core I/Os routed off-chip and slices optimized for area. Please contact CAST to get characterization data for your target configuration and technology.

Supported
Family
Slices

GCLK IOBs
Fmax
(MHz)
ISE
Version
Spartan-3E
3S1200E-5
236 1 39 146 12.2i
Spartan-6
6SLX25-3
83 1 39 169 12.2i
Virtex-5
5VLX30-3
94 1 39 280 12.2i
Virtex-6
6VLX130T-3
64 1 39 363 12.2i

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