H16450S Core — Intel Implementation Results

The H16450S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data optimized for speed. Please contact CAST to get characterization data for your target configuration and technology.

Supported
Family
Utilization I/Os Fmax
(MHz)
Quartus
Version
LEs BRAM
Cyclone
EP1C20-6
359 - 39 218  
Cyclone-II
EP2C70-6
345 - 39 172 7.2
Cyclone-III
EP3C40-6
350 - 39 208 7.2
Stratix-II
EP2S180-3
239 - 39 228 7.2
Stratix-III
EP3E260-4
238 - 39 171 7.2

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