- Three Independent 16-bit Counters
- Status Read-Back Command
- Counter Latch Command
- Read/Write LSB only or MSB only or LSB first then MSB
- Six Programmable Counter Modes
- Interrupt on Terminal Count
- Hardware Retriggerable One-Shot
- Rate Generator
- Square Wave Mode
- Software Triggered Strobe
- Hardware Triggered Strobe (Retriggerable)
- Binary or BCD Counting
- The C8254 was developed in HDL and synthesizes to approximately 4,200 gates depending on the technology used
- Functionality based on the INTEL 8254
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Related Information
News Releases
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- 06/09/97, CAST Releases New ASIC and DSP Cores
Articles
EDN - Cores arrive in a dozen
Electronic Engineering Times - Core Competency
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Peripherals IP Core C8254 Programmable Timer/Counter Core
The C8254 core implements a high performance programmable interval timer/counter device, which is designed to solve the common timing control problems in microcomputer system design. It provides three independent 16-bit counters, and each counter may operate in a different mode. All modes are software programmable. The C8254 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control programmed to match the requirements by programming one of the counters for the desired delay.
See representative implementation results (each in a new pop-up window):
Applications
The six programmable timer modes allow the C8254 to be used in applications requiring event counters including:
- elapsed time indicators
- programmable one-shots
Symbol Diagram

Block Diagram

Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The C8254 core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel 82C54 chip, and the results compared with the core’s simulation output.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench
- Simulation script, vectors, and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide

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