Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
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Application Processors
BA25 Adv. App. Processor
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Embedded Processors
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BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
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Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
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Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
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XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
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UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • Three Independent 16-bit Counters
  • Status Read-Back Command
  • Counter Latch Command
  • Read/Write LSB only or MSB only or LSB first then MSB
  • Six Programmable Counter Modes
    • Interrupt on Terminal Count
    • Hardware Retriggerable One-Shot
    • Rate Generator
    • Square Wave Mode
    • Software Triggered Strobe
    • Hardware Triggered Strobe (Retriggerable)
  • Binary or BCD Counting
  • The C8254 was developed in HDL and synthesizes to approximately 4,200 gates depending on the technology used
  • Functionality based on the INTEL 8254

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Downloads (PDFs)

Articles

EDN - Cores arrive in a dozen

Electronic Engineering Times - MPU peripheral cores roll

Electronic News - CAST Rolls Four Cores

C8254 Programmable Timer/Counter Core

The C8254 core implements a high performance programmable interval timer/counter device, which is designed to solve the common timing control problems in microcomputer system design. It provides three independent 16-bit counters, and each counter may operate in a different mode. All modes are software programmable. The C8254 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control programmed to match the requirements by programming one of the counters for the desired delay.

See representative implementation results (each in a new pop-up window):

Altera numbers Lattice numbers Xilinx numbers

Applications

The six programmable timer modes allow the C8254 to be used in applications requiring event counters including:

Symbol Diagram

C8254 Programmable Timer/Counter Symbol Diagram

Block Diagram

C8254 Programmable Timer/Counter Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The C8254 core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel 82C54 chip, and the results compared with the core’s simulation output.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

 

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