- Complies with ATA-8 Standard
- Supports one or two IDE devices
- Supports synchronous Ultra ATA-33, -66, -100 and -133
- Configurable parameters allow easy tailoring of core to specific application or implementation technology
- Programmable I/O modes:
0, 1, 2 and 4
- Multi-word DMA modes:
0, 1 and 2
- Generic SFR interface with configurable data bus: 8/16/32-bit
- Configurable Internal FIFO address bus width: min. 4-bit, no upper limit
- Configurable transmission counter size: from 2- to 32-bit
- OCP, AXI, AHB, PLB and Avalon interfaces
- DMA Controller provides synchronous data transmission interface
- Master and slave mode
- Scatter-gather support
- Configurable data bus: 8/16/32-bit
- Configurable address bus: min. 8-bit, no upper limit
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
Call or click.
- ATAIF-SD - a complete software set for handling the Parallel ATA host controller. It supplements the ATAIF controller with software elements and enables smooth integration of the controller in the target application, allowing user to easily access storage media of high capacity without detailed knowledge of the controller interface.
Advanced Technology Attachment
Learn more about ATA and its various standards with this WikiPedia entry.
Informal Info and History
See www.atapi-ata.com for information for developers of products using ATA (PATA, IDE/EIDE), Serial ATA (SATA), ATAPI, CF and other ATA related interfaces.
Storage IP Core ATAIF ATA/IDE/ATAPI ATA-8 Interface Core
Implements a host controller for non-volatile memory devices using the parallel interface known as ATA (Advanced Technology Attachment), IDE (Integrated Drive Electronics), and ATAPI (Advanced Technology Attachment Packet Interface). Complies with standard ATA-8.
The core provides a simple interface to memory devices such as hard-disk drives, DVD players, CDROM players/writers, Compact Flash storage, and PC Card devices. It supports PIO modes 0 to 4; Multi-word DMA modes 0, 1 and 2; Ultra ATA -33, -66, -100 and -133; and implements an interface to the IDE bus.
Developed for easy reuse in ASIC and FPGA implementations, the core is strictly synchronous, with positive-edge clocking, no internal tri-states, and a synchronous reset; scan insertion is straightforward.
See representative implementation results (each in a new pop-up window):
- IDE disk drive, CDROM player/writer & DVD player controllers
- Compact Flash and PC-Card readers
- Systems utilizing IDE/ATA and ATAPI drives for data storage including notebook and desktop computers, servers, set-top boxes and test equipment
- Data acquisition systems
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive simulation and rigorous code coverage measurements.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including an example system design and bus/behavioral model of interface stimulators
- Simulation script, vectors and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide