The following are sample ASIC pre-layout results, implemented without DRAM for the internal FIFO and using an ATA clock of 133 MHz.
| ASIC Technology | Logic Eq. Gates |
Processor Bus Clock Frequency |
| UMC 0.18µm1 | 14,100 | 100 MHz |
| UMC 0.18µm2 | 17,400 | 263 MHz |
| UMC 0.13µm2 | 18,500 | 500 MHz |
| UMC 0.09µm1 | 18,300 | 50 MHz |
Notes:
1 optimized for area
2 optimized for speed, using DMA Controller, max. size data buses,
and internal FIFO depth of 512 words