The megafunction has been evaluated in a variety of technologies. The following are sample Altera results with area optimized for speed, implemented with internal DMA controller, max. data bus sizes, and internal FIFO depth: 512 words.
| Altera Devices | Area | ATA Clock | Processor Bus Clock Frequency |
| Cyclone EP1C4 6 |
3430 LCs + 8 M4Ks | 100 MHz | 135 MHz |
| Stratix EP1S10 5 |
3900 LCs + 8 M4Ks | 133 MHz | 140 MHz |
| Stratix II EP2S15 3 |
3280 ALUT + 8 M4Ks | 133 MHz | 205 MHz |
| Cyclone II EP2C20 6 |
3630 LCs + 8 M4Ks | 133 MHz | 145 MHz |