SCVL

Standard Component VHDL Library

The Standard Component VHDL Library, SCVL, is a comprehensive, economical solution for system-level modeling with VHDL.

SCVL gives you easy-to-use models for thousands of the most popular components. Two packages are available:

• SCVL-L includes selected logic devices from the 54/74 standard parts series, and
• SCVL-M includes memories such as Static RAMs, ROMs, FIFOs, Synchronous FIFOs, Dynamic RAMs, SDRAMs, EDO DRAMs, EDRAMs, Flash Memories, Video RAMs, Double Data Rate Synchronous DRAM, and Synchronous SRAM.

All SCVL models fully conform to the IEEE 1076 VHDL standard, and they use high-level functions for optimal simulation performance.

Each model has built-in minimum, typical, and maximum (min/typ/max) timing values that you can select through VHDL generics. Violation checking for setup, hold, and pulse width times is also built in, with optional generation of "X" values. Violations are automatically reported to a file, or you can disable checking when desired for faster simulation of very large systems.

The models allow for timing back-annotation of input wire delays and load delays. Memory device models use dynamic memory allocation to minimize your system requirements.

SCVL models are delivered in a source-code form that lets you easily change the pin-to-pin timing data and create additional aliases. They are designed for easy regeneration to support any changes in applicable standards.

SCVL includes a 30-day warranty.