Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Built-in protection of code and data in a 32-bit compact, low-power, royalty-free, processor IP core.

Secure Execution

  • Protects sensitive code and data during execution, storage, and transfer to/from the processor
  • Uses two or more cryptographically isolated secure execution contexts
  • Agnostic to cryptographic primitives:
    • uses lowest-overhead Keccak-based (SHA3) crypto engine by default;
    • can alternatively support any cryptographic hash functions and symmetric cipher

Low-Power Operation

  • Extreme Code Density of the BA2x™ ISA minimizes instruction memory area and power consumption
  • Advanced Power Management
    • Dynamic clock gating and power shut-off of unused units
    • Software- and hardware-controlled clock frequency
    • Wake-up on tick timer or external interrupt
  • Small silicon footprint: just 35K gates on 90nm

Processing Efficiency

  • The processor core can be clocked at over 800 MHz in 28nm and 16nm processes

Optional Processor Units

  • Programmable Vectored Interrupt Controller Unit
  • Timer Unit
  • Debug Unit:MDB and Trace port support
  • ROM patching Unit
  • Floating Point Unit
  • Hardware Multiplier/Divider

Easy Software Development

  • Non-intrusive JTAG CPU and system debug/trace
  • Complex chained watchpoint and breakpoint conditions
  • BeyondStudio™ complete IDE for Windows or Linux (Eclipse)
  • Ported libraries and operating systems

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Options

Additional peripherals may be added before delivery of the core.

A hardware reference design board is available.

CAST Integration Services are available to help integrate this core with other CAST IP cores.

Try It Yourself

evaluate the BA22-DE 32-bit processor IP core from CAST with the Talos Eval KitEvaluate Geon's features and performance in your own environment with the Talos Series Evalation Kit.

Related Products

The BA2x™ Processor Family includes a set of royalty-free, pre-configured products intended for different applications:

Platforms

  • BA2x-AXI-PP pre-integrated peripherals platform for the AMBA3 AXI bus.
  • BA2x-AHB-PP pre-integrated peripherals platform for the AMBA2 AHB/APB buses.

Download our Controllers & Processors IP Overview (PDF).

Beyond Debug Key photoGet full diagnostics while developing embedded software for Geon processors with the JTAG Beyond Debug Key.

News Releases

Blog Posts

See more ba2x blog posts >>>

GeonSecure Execution Processor

The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data. It uses two or more cryptographically separated execution contexts for a high degree of security during code execution and for data storage and transfer to and from the processor.
Geon benefits from the extreme code density of the BA2xTM ISA, and employs advanced power management to further lower CPU and memory subsystem power consumption. It can be licensed without volume-based royalty fees.

Secure Execution with Geon

Geon addresses two fundamental security risks of modern SoC designs. First, it protects against breaches of confidentiality and integrity when firmware is stored outside or transferred to the processor. Geon does this by using authenticated encryption: code and data are only decrypted and checked for integrity at fetch time within the processor, and therefore are protected while they reside on the system memory or while being transferred to the processor.

Second, Geon protects against breaches of sensitive code and data from compromised software threads. For this it assigns address spaces and processor units to just one of the multiple secure execution contexts, and uses a separate set of encryption keys per execution context for the code and data encryption. In this manner, even a complete breach of a software thread in one execution context fails to compromise the data and code of the other contexts.

Processor Description

Geon implements a versatile and efficient 32-bit processor with five pipeline stages. It interfaces to main memory via separate instruction and data caches. It supports tightly coupled memories for fast and deterministic access to code and data, and its Memory Management Unit enables the use of virtual memory.

Geon connects to main memory and peripherals via 32-bit wide AMBA® AHB™ or AXI data and instruction buses. Its default configuration includes up to 32 general purpose registers, a tick-timer, a programmable interrupt controller, and an advanced power management unit. Options include modules for debug, floating point, vectored interrupt control, ROM patching, and hardware multiplication and division. The processor can be extended to execute the rich set of DSP extensions of the BA2x ISA, or to handle custom instructions using its inline coprocessor interface.

Applications

Designers using Geon get the benefit of robust protection of code and data in a compact, low-power processor core. Geon brings secure execution to embedded and deeply-embedded processors, and is suitable for the design of a wide-range of SoCs, especially wearable electronics and Internet of Things nodes for automotive, industrial, healthcare, and home automation applications.  

The BA2 Instruction Set

Geon supports the BA2x instruction set, which provides extreme code density without compromises in performance, ease of use, or scalability. It features:

Deliverables

The core is available for ASICs in synthesizable Verilog source code, and includes everything required for successful implementation. The core is delivered with software development tools Windows and Linux, with an Eclipse IDE interface.
Additional microcontroller peripherals may be ordered for pre-integration and delivery with the core, individually or in a complete platform. IP Integration Services are also available to help integrate the processor with memory controllers, image compression, or other CAST IP cores.

Support and Services

The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
IP Integration Services are also available to help minimize time to market for Geon-based systems.

 

 

 

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