Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

High Performance 32-bit CPU

  • Seven-Stage Pipeline
  • Out-of Order Completion
  • Sophisticated Branch Prediction
  • Optional Floating Point Unit
  • 1.51 DMIPS/MHz
  • 2.51 Coremarks/MHz
  • 800+ MHz on TSMC 65nm LP

Efficient Power Management

  • Dynamic clock gating and power shut-off of unused units
  • Software- and hardware-controlled clock frequency
  • Wake-up on tick timer or external interrupt

Fast & Flexible Memory Access

  • Separate Instruction and Data Caches and MMU
    • AXI4 data & instruction buses (32-, 64- or 128-bit) with 4 GBytes direct addressable space on each bus
  • Tightly coupled Quick Memory (QMEM) interface for fast and deterministic access to code and/or data

Two-Level Cache and MMU

  • L0 cache running at core frequency and L1 cache running at half the core frequency
  • 1–16 Kbytes L0 caches, up to
    four-way set associative
  • 32–512 Kbytes L1 caches, up to four-way set associative
  • L0 MMU with up to 32 four-way associative entries
  • L1 MMU with up to 2048 four-way associative entries

Optional Integrated Peripherals

  • Vectored Interrupt Controller
  • Microcontroller peripherals such as GPIO, UART, Real-Time Clock, Timers, I2C, and SPI
  • Memory controllers, interconnect IP, and more

Easy Software Development

  • Non-intrusive JTAG debug/trace for both CPU and system
  • Complex chained watchpoint and breakpoint conditions
  • BeyondStudio™ complete IDE for Windows or Linux under Eclipse
  • Ported libraries and operating systems

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Options

Additional peripherals may be added before delivery of the core.

A hardware reference design board is available.

CAST Integration Services are available to help integrate this core with other CAST IP cores.

Related Products

Compare
Versions

The BA2x™ Processor Family includes a set of royalty-free, pre-configured products intended for different applications:

Platforms

  • BA2x-AXI-PP pre-integrated peripherals platform for the AMBA3 AXI bus.
  • BA2x-AHB-PP pre-integrated peripherals platform for the AMBA2 AHB/APB buses.

Download our Controllers & Processors IP Overview (PDF).

Development Tools

Beyond Debug Key photoGet full diagnostics while developing embedded software for BA2x processors with the JTAG Beyond Debug Key.

It works with BeyondStudio, included with every BA2X Processor license. This Eclipse-based IDE extends the GNU C/C++ tools and provides special libraries and functions for rapid development with the BA2 instruction set architecture.

The BA2X Processor Family is also supported by the Trace32® Debugger from Lauterbach.

Try It YourselfTry the BA22-DE 32-bit MCU IP core from CAST with the Talos Eval Kit

Evaluate the features and performance of this BA2X Processor in your own environment with the Talos Series Evaluation Kit.

Articles

CAST: feeling the DesignCon vibe
EDACafe, Peggy Aycinena, 1/30/2013

DesignCon 2013 Yields IP, RF, DoE, and Mind Surprises
IP Insider, John Blyler, 2/1/2013

CAST announces royalty-free BA22 32-bit RISC IP
EDN Network, Ron Wilson, 8/3/2011

Blog Posts

See more ba2x blog posts >>>

BA2532-bit Application Processor

Implements a 32-bit processor for demanding systems running applications on general-purpose operating systems such as Linux and Android. The high-performance BA25™ processor runs at high clock frequencies yet has a smaller silicon footprint than most competing application processors (e.g., over 800MHz and from 150Kgates in TSMC65nmLP, 12-track library).

This royalty-free 32-bit processor core is binary-compatible with other members of the silicon-proven BA2x processor family. Its BA2 instruction set is relatively simple and extremely compact, offering system area and energy savings benefits. Programing is facilitated with the included C/C++ tool chain, Eclipse IDE, architectural simulator, and ported C libraries, RTOSs, and OSs.

Processor Description

The seven-stage pipelined architecture runs at high frequencies and further enhances performance by supporting out-of-order execution and branch prediction. An optional IEEE 754 compliant floating-point unit accelerates floating point computation.

BA25 Block Diagram The BA25 processor uses two-level data and instruction caches—with L0 running at the CPU’s clock frequency and L1 running at half that—and a two-level memory management unit. The size and associativity of the caches and MMU are configurable at synthesis time. The system interface uses two AMBA® AXI4 buses, one for data and one for instructions, both of configurable data width. Two tightly-coupled quick memory (QMEM) buses allow fast access for time-critical code and data, and can be used for inter-core communication in a multi-core architecture.

The energy efficiency BA25 enables power management with clock gating and power shut-off of unused units, and through software and hardware control over the clock frequency of the CPU and buses. Wake-up from sleep mode is triggered by an interrupt issued by the embedded tick-timer or by an external source. Rapid interrupt response is facilitated by the embedded programmable vectored interrupt controller.

Applications

The royalty-free, high-performance BA25 processor core is suitable as the main system processor in a multitasking environment and is a competitive choice for designs running on full operating systems such as Linux or Android. Target product types include:

The BA2 Instruction Set

The BA2 instruction set provides extreme code density without compromises on performance, ease of use, or scalability. It features:

Customizable Platforms

The BA25 processor can be delivered pre-integrated with typical microcontroller peripherals such us UARTs, timers and serial communication cores, or with memory controllers and interconnect IP cores. Contact CAST Sales for details.

Support and Services

The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

IP Integration Services are also available to help minimize time to market for BA25-based systems.

Deliverables

The core is available for ASICs in synthesizable Verilog source code, and includes everything required for successful implementation. The core is delivered with software development tools Windows and Linux, with an Eclipse IDE interface.

Related Products

The BA2™ Processor Family includes a set of royalty-free, pre-configured products intended for different applications:

Comparing BA2x Family Processor Cores

Features

BA20
PipelineZero
Embedded
BA21
Low-Power
Deeply Embedded

BA22-DE
Deeply
Embedded

BA22-CE
Cache-Enabled
Embedded

BA22-AP
Basic Application
Processor

BA25
Application
Processor

BA2 Variable Length ISA

included

included

included

included

included

included

Pipeline Stages

1

2

4/5

5

5

71 / 12

Out of Order Completion

optional

optional

not supported

not supported

not supported

included

Branch Prediction Unit

not supported

not supported

optional

optional2

optional2

included

Memory Protection Unit

optional3

optional

optional2

optional2

not supported

not supported

Number of GPRs

12-32

12-32

16/32

16/32

32

32

SoC Data Bus

EMEM/AXI4 Lite

EMEM/AXI4 Lite

AHB/WB/AXI42

AHB/WB/AXI42

AHB/WB/AXI42

AXI4

SoC Instruction Bus

EMEM/AXI4 Lite

EMEM/AXI4 Lite

AHB/WB/AXI42

AHB/WB/AXI42

AHB/WB/AXI42

AXI4

Hardware Multiplier and/or Divider

optional

optional

optional

included

included

included

Multiply-Accumulate Unit

optional2

optional2

optional

optional

optional

optional

Floating Point Unit

optional2

optional2

optional

optional

optional

optional

DSP Extensions Acceleration

not supported

optional2

optional

optional

optional

optional

JTAG Debug Support

optional

optional

optional

optional

optional

optional

Embedded Tick Timer, PIC, and PMU

optional

optional

optional

included

included

included

Vectored Interrupt Controller

optional

optional

optional

optional

optional

optional

Tightly Coupled I/D Busses

included

included

included

optional

optional

optional

Instr. & Data Caches

not supported

not supported

not supported

included(L0)

included(L0)

included(L0/L1)

Instr. & Data MMU

not supported

not supported

not supported

not supported

included(L0)

included(L0/L1)

Configurable Peripherals Platform

optional

optional

optional

optional

optional

optional

Beyond Studio SW IDE and GCC SDK

included

included

included

included

included

included

DMIPS/MHz

1.52/1.99/3.044

1.49/2.335

1.76/2.535

1.76/2.536

1.76/2.536

1.51

CoreMarks/MHz

3.41

2.77

2.93

2.936

2.936

2.51

FMAX @ TSMC65LP

75 MHz

150 MHz

400 MHz

400 MHz

400 MHz

800 MHz

Eq. Gates5

From 10k

From 10k

From 15k

From 25k

From 35k

From 150k

Availability

Now

Now

Now

Now

Now

Now

Royalty Free Licensing

optional

optional

optional

optional

optional

optional

included= Supported   optional= Optional   not supported= Not Supported

Notes:

1) Minimum for simple ALU instructions.
2) Feature can be made available up on request.
3) Work in progress.
4) DMIPS rating using GCC v4.9.1 and ground rules/optimizations/link-time optimizations
3) DMIPS rating using GCC v4.9.1 and optimizations, link-time optimizations.
4) DMIPS rating for code running from tightly-coupled memories.

 

 

 

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