BA22-DE Core — ASIC Implementation Results

The BA22-DE can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Area, power and speed depend on configuration, optimizations, process, and libraries. Furthermore power consumption depends on power management, software and memories configuration. Please contact CAST to get characterization data for your target configuration and technology.

ASIC
Technology
Freq.
(MHz)
Area
(µm2)
Logic Eq.
Gates
TSMC 180nm (wl30, typ)
50
266,647.6
16,032
170
392,804.6
23,617
TSMC 130nm (wl30, typ)
50
148,828.0
17,536
150
186,841.3
22,015
225
297,593.3
35,064
TSMC 90nm (wl30, typ)
50
76,719.9
15,532
100
84,013.7
17,009
TSMC 65nm (wl30, typ)
50
46,671.6
11,668
200
65,960.0
16,490
380
127,420.4
31,855

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