BA22-DE Core — Intel Implementation Results

The BA22-DE can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following results reported from Intel tools, assume a 4kx64 RAM connected to the IQEM bus, an 8kx32 RAM con-nected to the DQEM bus, that all clocks are driven by a common source, and that all core I/Os are routed off-chip. The provided figures do not represent the higher speed or smaller area for the core. Area, power and speed depend on core configuration and tool optimizations. Furthermore power consumption depends on power management, software and memories configuration. Please contact CAST to get characterization data for your target configuration and technology.

Family
Device
Logic Area Freq.
(MHz)
Memory*
Cyclone IV-E
EP4CE75F29C6
5,845 LEs
63
66 M9Ks
Cyclone V
5CGXFC7D6F31C6
3,299 ALUTs
76
66 M10Ks
Stratix IV
EP4SE820H35C3
3,338 ALUTs
115
66 M9Ks
Stratix V
5SGXMA7H1F35C1
3,459 ALUTs
153
34 M20Ks
* Memory required for the implementation of QMEMs, not he CPU.

close window