BA22-CE Core — Xilinx Implementation Results

The BA22-CE can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following results reported from Xilinx tools, assume 32 GPRs, a 4kx64 RAM connected to the IQEM bus, an 8kx32 RAM connected to the DQEM bus, a 8Kbytes 2-way associa-tive instruction cache, a 2Kbytes 2-way associative data cache, that all clocks are driven by a common source, and that all core I/Os are routed off-chip. The provided figures do not represent the higher speed or smaller area for the core. Area, power and speed depend on core configuration and tool optimizations. Furthermore power consumption depends on power management, software and memories configuration. Please contact CAST to get characterization data for your target configuration and technology.

Family
Device
Logic
(Slices)
Freq.
(MHz)
Memory*
(BRAM)
Spartan-6
XC6SLX150T-3
1,988
91
38
Virtex-6
XC6SLX130T-3
2,336
128
40
* Memory required for the implementation of QMEMs and caches, not he CPU.

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