BA22-CE Core — ASIC Implementation Results

The BA22-CE can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. Implementation numbers are for the core implemented with 4-way associative cache memories. The provided results do not represent the higher speed or smaller area for the core and area figures do not include the cache RAM size. Please contact CAST to get characterization data for your target configuration and technology.

ASIC
Technology
Freq.
(MHz)
Area
(µm2)
Logic Eq.
Gates
TSMC 130nm (wl30, typ)
50
241195.4
28,419
150
286847.0
33,798
225
431501.1
50,842
TSMC 90nm (wl30, typ)
50
126612.9
25,634
150
146659.0
29,692
200
165317.8
33,470
TSMC 65nm (wl30, typ)
50
75978.4
18,994
200
100748.4
25,187
300
144512.0
36,128

Area, power and speed depend on configuration, optimizations, process, and libraries. Furthermore power consumption depends on power management, software and memories configuration.

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