BA22-CE Core — Intel Implementation Results

The BA22-CE can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following results reported from Intel tools, assume 32 GPRs, a 4kx64 RAM connected to the IQEM bus, an 8kx32 RAM connected to the DQEM bus, a 8Kbytes 2-way associa-tive instruction cache, a 2Kbytes 2-way associative data cache, that all clocks are driven by a common source, and that all core I/Os are routed off-chip. The provided figures do not represent the higher speed or smaller area for the core. Area, power and speed depend on core configuration and tool optimizations. Furthermore power consumption depends on power management, software and memories configuration. Please contact CAST to get characterization data for your target configuration and technology.

Family
Device
Logic Area Freq.
(MHz)
Memory*
Cyclone IV-E
EP4CE75F29C6
8,788 LEs
58
84 M9Ks
Cyclone V**
5CGXFC7D6F31C6
4,696 ALUTs
90
84 M10Ks
Stratix IV
EP4SE820H35C3
5,437 ALUTs
131
82 M9Ks
Stratix V
5SGXMA7H1F35C1
5,203 ALUTs
153
50 M20Ks
* Memory required for the implementation of QMEMs and chaches, not he CPU.
** CycloneV implementation does not include the debug unit.

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