BA22-AP Core — ASIC Implementation Results

The BA22-AP can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following are sample ASIC pre-layout results re-ported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. Implementation numbers are for the core implemented with 4-way associative cache memories, 4-way associative MMUs and without an FPU. The provided figures do not represent the higher speed or smaller area for the core and area figures do not include the cache and MMU RAM size. Please contact CAST to get characterization data for your target configuration and technology.

ASIC
Technology
Freq.
(MHz)
Area
(µm2)
Logic Eq.
Gates
TSMC 90nm
(wl30, typ)
50
172,701
34,965
150
179,021
36,245
200
187,194
37,900

Area, power and speed depend on configuration, optimizations, process, and libraries. Furthermore power consumption depends on power management, software and memories configuration.