Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Ultra-Low Power

  • PipelineZero™ architecture for high performance efficiency with tiny silicon footprint
    • 3.04 DMIPs/MHz
    • 3.41 Coremarks/MHz
    • 2uW/MHz and 10K gates (0.01mm2) in 9-track 40G
  • BA2™ ISA Extreme Code Density for less instruction fetching energy usage
  • Advanced power management
    • Dynamic clock gating and power shut-off of unused units
    • Software- and hardware-controlled clock frequency
    • Wake-up on tick timer or external interrupt

Optional Processor Units

  • Programmable Vectored Interrupt Controller Unit
  • Memory Protection Unit
  • Timer Unit
  • Debug Unit
    • MDB support
    • Trace port support
  • ROM Patching Unit
  • Floating Point Unit
  • Hardware Multiplier/Divider

Pre-Integrated Platforms

  • Available microcontroller peripherals include GPIO, UART, Real-Time Clock, Timers, I2C, and SPI
  • Memory controllers, inter­connects, and more from the CAST IP line

Easy Software Development

  • Non-intrusive JTAG or Serial debug/trace for both CPU and system
  • Complex chained watchpoint and breakpoint conditions
  • BeyondStudio™ complete IDE for Windows or Linux under Eclipse
  • Ported libraries and operating systems

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

 

The BA2x Family of Processors

The BA2x™ Processor Family includes a set of royalty-free, pre-configured products intended for different applications:

Compare
Versions

  • BA21 32-bit Low-Power Deeply Embedded Processor, a dual-pipeline 32-bit low-power processor that delivers better performance than most processors its size.

  • BA22-DE 32-bit Deeply Embedded Processor, a 4- or 5-stage pipelined processor for deeply embedded applications that use on-chip instruction and data memories.

  • BA22-CE 32-bit Cache-Enabled Embedded Processor,a 4- or 5-stage pipelined processor, with instruction and data caches for deeply embedded applications.

  • BA22-AP Basic Application Processor, a 5-stage pipelined, cache, and MMU-enabled processor.

  • BA25 Advanced Application Processor, a 7/12-stage pipelined, out of order, cache- and MMU-enabled processor.

Platforms

  • BA2x-AXI-PP pre-integrated peripherals platform for the AMBA3 AXI bus.
  • BA2x-AHB-PP pre-integrated peripherals platform for the AMBA2 AHB/APB buses.

Download our Controllers & Processors IP Overview (PDF).

Beyond Debug Key photoGet full diagnostics while developing embedded software for BA2x processors with the JTAG Beyond Debug Key.

News Releases

 

Blog Posts

See more ba2x blog posts >>>

BA20 PipelineZero 32-bit Embedded Processor

Implements a small, ultra-low-power, and very processing-efficient 32-bit processor, ideal for energy-sensitive deeply embedded applications such as wearable electronics, Internet of Things (IoT) sensors, wireless communication, and other mixed-signal ICs.

BA20 Block Diagram

Thanks to its PipelineZero™ architecture, the BA20 core delivers a surprisingly high processing efficiency with a tiny silicon footprint. True single-cycle instruction execution of the BA2 ISA, zero-delay branches, no pipeline-stalling overheads, and an optional hardware multiply unit enable the BA20 to operate with efficiency as high as 3.41 CoreMarks/MHz. With no pipeline stages in the instruction execution path the BA20 uses a minimal number of flip-flops and a simplified CPU control, so its processing efficiency comes without a silicon area penalty. For example, in a 40G technology the BA20 occupies about 10,000 gates, or approximately 0.01mm2.

These advantages plus advanced power management features and the extreme code density of the BA2 instruction set make the BA20 the most energy-efficient 32-bit processor currently available, consuming just 2uW/MHz on a 40G technology.

The BA20’s capabilities can be enhanced with options including a hardware multiplier/divider, multiply-accumulate block, and IEEE 754 compliant floating-point units. A vectored interrupt controller facilitates timely responses to interrupts, and an optional memory protection unit protects application code and/or data from corruption.

The core’s system interface uses a 32-bit wide AMBA® AXI4-lite bus. Two tightly-coupled embedded memory (EMEM) buses allow fast access for time-critical code and data, and can be used for inter-core communication in a multi-core architecture. Software development is facilitated with the included C/C++ tool chain, BeyondStudio™ Eclipse-based IDE, architectural simulator, ported C libraries, RTOSs and OSs, debug capabilities, and hardware reference designs.

Additional microcontroller peripherals may be ordered for pre-integration and delivery with the core, individually or in a complete platform.

The BA2 Instruction Set

The BA2 instruction set provides extreme code density without compromising performance, ease of use, or scalability. It features:

Customizable Platforms

The BA20 processor can be delivered pre-integrated with typical microcontroller peripherals such us UARTs, timers and serial communication cores, or with memory controllers and interconnect IP cores. Contact CAST Sales for details

Support and Services

The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. IP Integration Services are also available to help minimize time to market for BA22-based systems.

Deliverables

The core is available for ASICs in synthesizable Verilog source code or FPGAs in optimized netlists, and includes everything required for successful implementation. The core is delivered with software development tools for Windows and Linux, with an Eclipse IDE interface.

Comparing BA2x Family Processor Cores

Features

BA20
PipelineZero
Embedded
BA21
Low-Power
Deeply Embedded

BA22-DE
Deeply
Embedded

BA22-CE
Cache-Enabled
Embedded

BA22-AP
Basic Application
Processor

BA25
Application
Processor

BA2 Variable Length ISA

included

included

included

included

included

included

Pipeline Stages

1

2

4/5

5

5

71 / 12

Out of Order Completion

optional

optional

not supported

not supported

not supported

included

Branch Prediction Unit

not supported

not supported

optional

optional2

optional2

included

Memory Protection Unit

optional3

optional

optional2

optional2

not supported

not supported

Number of GPRs

12-32

12-32

16/32

16/32

32

32

SoC Data Bus

EMEM/AXI4 Lite

EMEM/AXI4 Lite

AHB/WB/AXI42

AHB/WB/AXI42

AHB/WB/AXI42

AXI4

SoC Instruction Bus

EMEM/AXI4 Lite

EMEM/AXI4 Lite

AHB/WB/AXI42

AHB/WB/AXI42

AHB/WB/AXI42

AXI4

Hardware Multiplier and/or Divider

optional

optional

optional

included

included

included

Multiply-Accumulate Unit

optional2

optional2

optional

optional

optional

optional

Floating Point Unit

optional2

optional2

optional

optional

optional

optional

DSP Extensions Acceleration

not supported

optional2

optional

optional

optional

optional

JTAG Debug Support

optional

optional

optional

optional

optional

optional

Embedded Tick Timer, PIC, and PMU

optional

optional

optional

included

included

included

Vectored Interrupt Controller

optional

optional

optional

optional

optional

optional

Tightly Coupled I/D Busses

included

included

included

optional

optional

optional

Instr. & Data Caches

not supported

not supported

not supported

included(L0)

included(L0)

included(L0/L1)

Instr. & Data MMU

not supported

not supported

not supported

not supported

included(L0)

included(L0/L1)

Configurable Peripherals Platform

optional

optional

optional

optional

optional

optional

Beyond Studio SW IDE and GCC SDK

included

included

included

included

included

included

DMIPS/MHz

1.52/1.99/3.044

1.49/2.335

1.76/2.535

1.76/2.536

1.76/2.536

1.51

CoreMarks/MHz

3.41

2.77

2.93

2.936

2.936

2.51

FMAX @ TSMC65LP

75 MHz

150 MHz

400 MHz

400 MHz

400 MHz

800 MHz

Eq. Gates5

From 10k

From 10k

From 15k

From 25k

From 35k

From 150k

Availability

Now

Now

Now

Now

Now

Now

Royalty Free Licensing

optional

optional

optional

optional

optional

optional

included= Supported   optional= Optional   not supported= Not Supported

Notes:

1) Minimum for simple ALU instructions.
2) Feature can be made available up on request.
3) Work in progress.
4) DMIPS rating using GCC v4.9.1 and ground rules/optimizations/link-time optimizations
3) DMIPS rating using GCC v4.9.1 and optimizations, link-time optimizations.
4) DMIPS rating for code running from tightly-coupled memories.

 

 

 

tw    fbk    li    li    li
Top of Page