Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.
   Stack

IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

CMOS or CCD sensor interface, delivering quality-optimized RGB or YUV images ready for display, compression or further processing

Processing Pipeline

  • Bayer Interpolation/De-mosaicing
  • RGB to YUV Conversion
  • Visual Quality Enhancements
    • White Balancing
    • Contrast Stretching (Normalization)
    • Gamma Correction
    • Sharpening Filter

Low-Power with Low Latency

  • Minimal buffering for low-latency and low-power operation
    • Only five lines of buffering under its full configuration (two for Bayer filtering, and three for image sharpening)
  • Optimized, small implementation requires less than 15,000 equivalent gates

Performance

  • Fine pipeline allows processing up to over 150 Mpixels/sec even in low-end silicon

Input/Output Formats

  • 10bit/sample Raster-Scan Bayer Input, 8bit/Sample-Raster-Scan YUV Output
  • Up to two Mpixels, optionally extendable for higher resolution

Maturity

  • Robustly verified and production proven

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

News Releases

CAMFECamera Front-End Processor Core

The CAMFE Core implements a flexible, resource-efficient camera front-end processor that receives raw pixel data from a CMOS or CCD sensor and outputs a video stream ready for display, further processing, or compression.

The core first converts the Bayer pattern output from the sensor to an RGB image using an efficient de-mosaicing interpolation filter. The interpolated RGB samples are input to the White Balancing stage, which adjusts color intensities so they are appropriate for reproduction in a display. Under its full configuration, the core subsequently proceeds with further steps essential for optimizing the visual quality of the image, running RGB to YUV color space conversion, then performing Contrast Stretching (also called Normalization) and Gamma Correction, and finally applying a Sharpening Filter.

The CAMFE Core requires only a few lines of buffering and adds minimal processing latency. It features extremely low power consumption due to the absence of a power-consuming frame buffer and the core’s small silicon footprint (less than 15,000 gates). Furthermore, a fine-pipelined structure allows CAMFE to operate at high clock frequencies, and it can process over 150 Mpixels/sec even in low-end FPGAs.

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Applications

The CAMFE is suitable for interfacing a CMOS or CCD sensor in a variety of applications that display, process or compress images such as medical imaging, surveillance, autonomous or unmanned vehicles, biometrics analysis, and video streaming.

Block Diagram

CAMFE Camera Front-End Processor IP Core Block Diagram

Example Output

Photos showing the image improvements made by the Camera Front End Processor (CAMFE) IP Core from CAST. with applications of Bayer Filter, White Balance, Contrast Stretching, Gamma Correction, and Sharpening Filter.

(Click to see a higher-resolution version.)

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

 

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