80186EC IP Core C80188EC Intel® 80C188EC-Compatible 16-bit Microcontroller Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Example Application | Support | Verification | Deliverables

Implements a pin-compatible replacement for the Intel® 80C188EC chip.

It is Identical to the C80186EC but has an 8-bit rather than a 16-bit system interface for compatibility with 8-bit architectures. A single-chip, high-performance, 16-bit microcontroller, the core executes the widely-known instruction set of Intel 80c86 or 80c186 devices. It has an extended peripheral set with three timers, two serial units, a watchdog timer, two universal interrupt controllers (8259a) and four DMA channels.

Compatibility with the original chip was ensured using hardware modeler-based reverse engineering. Software written for the original chip should execute on the C80188EC with little or no additional effort. A set of flexible outputs makes it easy to ensure pin-to- pin compatibility using current ASIC or FPGA fabrication technologies, making obsolete part replacement straightforward and cost-effective for either low- or high-volume applications.

The microcode-free core design is strictly synchronous, with positive-edge clocking, no internal tri-states, and a synchronous reset; therefore scan insertion is straightforward. Customers have successfully used this core to replace obsolete chips.

See representative implementation results (each in a new pop-up window):

Features

• Control Unit:
• 9-level deep and 1-byte wide instruction queue
• Independent instruction execution stages allow instructions to overlap
• Arithmetic Logic Unit:
• 16-bit arithmetic and logical operations
• Boolean manipulations
• 16 x 16-bit multiplication and 32-/16-bit division
• Memory Interface:
• compliant with the 80c1886ec device
• 20-bit addressing space
• 1MB memory space divided into 64KB logical segments
• Internal and external control of the length of memory access to instruction and data
• 64KB IO space
• Chip Select Unit with ten chip select outputs for use with memory devices
• Peripheral Control Block:
• 128 16-bit wide words predefined for peripherals control
• Programmable into memory or IO space
• Power Management Unit enabling clock division by 1,4,8, 16, 32 and 64 factors
• Three 16-bit Timers/Counters
• Watchdog Timer
• Direct Memory Access (DMA) Controller:
• Four separate, full-functional DMA channels
• External transfer initiation by DRQn pins
• Linear access to 20-bit memory addressing space
• Two USART Peripheral Interfaces in full duplex mode:
• Synchronous and asynchronous transmission
• Full-duplex operation
• 7-, 8- or 9-bit data transfers
• Odd, even, or no parity
• Clear to send feature in transmission
• Double buffered TX/RX
• Programmable Interrupt Controller:
• Two internally cascaded 8259a interrupt controllers
• Nine external interrupt lines, including NMI
• Seven internal interrupts generated by peripherals
• Refresh Control Unit
• Strictly synchronous design with no internal tri-states

Applications

The C80188EC is designed for obsolete parts replacement, but can also serve well in embedded systems or as a new controller (because it requires little extra support from a chipset). Suitable applications include high-speed control systems, microcomputer systems, automotive controls, and audio and video controls.

Block Diagram

Functional Description

The C80188EC core is partitioned into modules as shown in the figure above and described below.

C80186 CPU

This module consists of several smaller parts. The Arithmetic Logic Unit (ALU) is capable of conducting 16-bit arithmetic and logic operations as well as arithmetic and logic shift operations. The Multiplication Division Unit (MDU) increases performance and flexibility of the core by executing 16X16 multiplication, and 32/16 division (signed and unsigned). The control subcomponent contains the instruction decoder and the main Finite State Machine (FSM), while the Queue component, eight bits wide and five levels deep, fetches all instructions and immediate data. The C80186CPU has the control logic for memory interface, as well as general purpose segment, index, base pointer and status registers.

Internal Timer Unit

This Timer Unit has three programmable Timers\Counters. Timer 0 and 1 are 16-bit versatile timers and external event counters, each with two external pins, input and output. Timer 2 is also a 16-bit timer for internal use, such as generating delays, and is not connected to the external pin.

Serial0, Serial1

The Serial Unit is comprised of two identical serial ports; each serial port operates independently from the other. The serial interfaces provide flexible, full-duplex synchronous/asynchronous receiver/transmitter operations. Each module can operate in five modes, one synchronous and four asynchronous. Both serial units are buffered at the receive side, and also at the transmit side.

Refresh Control Unit

Generates refresh addresses for the external DRAM memory, with request time intervals programmable by a 9-bit register.

Four DMA channels

The Direct Memory Access unit is comprised of two identical modules with two DMA channels each. The DMA transfers allow for data coping without processor intervention. The DMA unit can be configured for transfer from/to different addresses and from/to memory or the I/O space, with the address increment/decrement option different for the source and the destination.

Interrupt Control Unit

Comprised of two 8259A modules connected in a cascade. Each instance of the 8259A module is implemented as an independent IP compatible with the Intel® 8259A chip.

PWRMAN

Gathers logic related to clock generation, clock divide, and reset generation. Since this type of logic can be technology-dependent, PWRMAN is outside the core.

Chip Select Unit

A set of comparators used to activate the appropriate chip select signal, depending on a current address and the control register configuration. It also generates an internal acknowledge signal, depending on the external acknowledge signal and internally-generated wait states.

Watchdog

Can preserve a system from an unexpected software dead loops or/and critical system errors. Contains a down counter that should be reloaded periodically or it signals underflow. Such an event can be used to interrupt the microcontroller or cause a system reset.

Example Application

The 80188EC architecture suits low-power or low-pin applications if overall system performance is not a key factor. Here data read from sensors using serial transmission can be processed and the results may be stored in the internal NAND Flash memory or visualized on an LCD screen using the VGA Controller. Data may be uploaded to the storage device at any moment using the USB or Firewire interfaces. 

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The C80188EC core’s instruction set functionality as well as the peripherals set were verified by means of a proprietary Personal Hardware Modeler. The same instructions and test scenarios were put as stimulus to a hardware model that contained the original Intel 80c186ec chip and the results of the operations were compared with the core’s simulation output.  Subsequently, pin-to-pin compatibility was achieved.

Deliverables

The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation:

• VHDL/Verilog source code (soft core) or a post-synthesis EDIF netlist (firm core)
• Example CHIP80188EC module. This chip level design uses the C80188EC IP core and illustrates how to build the module that is the pin replacement of the 80c188ec device
• Extensive stand alone  VHDL Testbench
• Simulation script, vectors, expected results, and comparison utility
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including detailed specifications and a system integration guide

 

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Example Application | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx