80188EC IP Core C80188EC Intel® 80C188EC-Compatible 16-bit Microcontroller Core

Implements a pin-compatible replacement for the Intel® 80C188EC chip.

It is Identical to the C80186EC but has an 8-bit rather than a 16-bit system interface for compatibility with 8-bit architectures. A single-chip, high-performance, 16-bit microcontroller, the core executes the widely-known instruction set of Intel 80c86 or 80c186 devices. It has an extended peripheral set with three timers, two serial units, a watchdog timer, two universal interrupt controllers (8259a) and four DMA channels.

Compatibility with the original chip was ensured using hardware modeler-based reverse engineering. Software written for the original chip should execute on the C80188EC with little or no additional effort. A set of flexible outputs makes it easy to ensure pin-to- pin compatibility using current ASIC or FPGA fabrication technologies, making obsolete part replacement straightforward and cost-effective for either low- or high-volume applications.

The microcode-free core design is strictly synchronous, with positive-edge clocking, no internal tri-states, and a synchronous reset; therefore scan insertion is straightforward. Customers have successfully used this core to replace obsolete chips.

See representative implementation results (each in a new pop-up window):

Applications

The C80188EC is designed for obsolete parts replacement, but can also serve well in embedded systems or as a new controller (because it requires little extra support from a chipset). Suitable applications include high-speed control systems, microcomputer systems, automotive controls, and audio and video controls.

Block Diagram

Example Application

The 80188EC architecture suits low-power or low-pin applications if overall system performance is not a key factor. Here data read from sensors using serial transmission can be processed and the results may be stored in the internal NAND Flash memory or visualized on an LCD screen using the VGA Controller. Data may be uploaded to the storage device at any moment using the USB or Firewire interfaces. 

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The C80188EC core’s instruction set functionality as well as the peripherals set were verified by means of a proprietary Personal Hardware Modeler. The same instructions and test scenarios were put as stimulus to a hardware model that contained the original Intel 80c186ec chip and the results of the operations were compared with the core’s simulation output.  Subsequently, pin-to-pin compatibility was achieved.

Deliverables

The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation:

• VHDL/Verilog source code (soft core) or a post-synthesis EDIF netlist (firm core)
• Example CHIP80188EC module. This chip level design uses the C80188EC IP core and illustrates how to build the module that is the pin replacement of the 80c188ec device
• Extensive stand alone  VHDL Testbench
• Simulation script, vectors, expected results, and comparison utility
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including detailed specifications and a system integration guide

This core is sourced from the IP experts at Evatronix SA.