- Control Unit:
- 9-level deep and 1-byte wide instruction queue
- Independent instruction execution stages allow instructions to overlap
- Arithmetic Logic Unit:
- 16-bit arithmetic and logical operations
- Boolean manipulations
- 16 x 16-bit multiplication and 32-/16-bit division
- Memory Interface:
- compliant with the 80c186xl device
- 20-bit addressing space
- 1MB memory space divided into 64KB logical segments
- Internal and external control of the length of memory access to instruction and data
- 64KB IO space
- Chip Select Unit with ten chip select outputs for use with memory devices
- Peripheral Control Block:
- 128 16-bit wide words predefined for peripherals control
- Programmable into memory or IO space
- Power Management Unit enabling clock division by a factor of 1, 4, 8, or 16
- Three 16-bit Timers/Counters
- Direct Memory Access (DMA) Controller:
- Two separate, fully-functional DMA channels
- External transfer initiation by DRQn pins
- Linear access to 20-bit memory addressing space
- Programmable Interrupt Controller:
- Five external interrupt lines, including NMI
- Five internal interrupts generated by the peripherals set
- Refresh Control Unit
- Optionally works with C80187 Math Coprocessor to speed floating-point calculations
- Strictly synchronous design with no internal tri-states
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Additional information:
Intel 80186 Wikipedia
80186XL IP Core C80186XL 80186XL-Compliant Chip Replacement 16-bit Microcontroller Core
A semiconductor IP core that implements a pin-compatible replacement for the Intel® 80C186XL chip.
This 80186XL ISA compliant 16-bit microcontroller is a single-chip, high-performance design that executes the widely-known instruction set of Intel 80c86 or 80c186 devices. It has the extended peripherals set of the 80C186XL: three timers, a refresh control units, and two direct memory access (DMA) channels.
Compatibility with the original chip was ensured using hardware modeler-based reverse engineering. Software written for the original chip should execute on the C80186XL with little or no additional effort. A set of flexible outputs makes it easy to ensure pin-to-pin compatibility using current ASIC, Structured ASIC, or FPGA fabrication technologies, making obsolete part replacement straightforward and cost-effective for either low- or high-volume applications.
The microcode-free core design is strictly synchronous, with positive-edge clocking, no internal tri-states, and a synchronous reset; therefore scan insertion is straightforward.
See representative implementation results (each in a new pop-up window):
Applications
The C80186XL is designed for obsolete parts replacement, but can also serve well in embedded systems or as a new controller (because it requires little extra support from a chipset). Suitable 16-bit applications include high-speed control systems, microcomputer systems, automotive controls, and audio and video controls.
Block Diagram
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The C80186XL core’s instruction set functionality as well as the peripherals set were verified by means of a proprietary Personal Hardware Modeler. The same instructions and test scenarios were put as stimulus to a hardware model that contained the original Intel 80c186xl chip and the results of the operations were compared with the core’s simulation output. Subsequently, pin-to-pin compatibility was achieved.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
- Example CHIP80186XL module.
This chip level design uses the C80186XL IP core and illustrates how to build the module that is the pin replacement of the 80c186xl device - Sophisticated HDL Testbench
- Simulation script, vectors, expected results, and comparison utility
- Synthesis (soft) or place and route (firm) script
- Comprehensive user documentation, including detailed specifications and a system integration guide
This core is sourced from the IP experts at Evatronix SA.
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