- Control Unit:
- 9-level deep and 1-byte wide instruction queue
- Independent instruction execution stages allow instructions to overlap
- Arithmetic Logic Unit:
- 16-bit arithmetic and logical operations
- Boolean manipulations
- 16 x 16-bit multiplication and 32-/16-bit division
- Memory Interface:
- compliant with the 80c186ec device
- 20-bit addressing space
- 1MB memory space divided into 64KB logical segments
- Internal and external control of the length of memory access to instruction and data
- 64KB I/O space
- Chip Select Unit with ten chip select outputs for use with memory devices
- Peripheral Control Block:
- 128 16-bit wide words predefined for peripherals control
- Programmable into memory or I/O space
- Power Management Unit enabling clock division by a factor of 1, 4, 8, 16, 32 and 64 factors
- Three 16-bit Timers/Counters
- Watchdog Timer
- Direct Memory Access (DMA) Controller:
- Four separate, fully-functional DMA channels
- External transfer initiation by DRQn pins
- Linear access to 20-bit memory addressing space
- Two USART Peripheral Interfaces in full duplex mode
- Synchronous and asynchronous transmission
- Full-duplex operation
- 7-, 8- or 9-bit data transfers
- Odd, even, or no parity
- Clear to send feature in transmission
- Double buffered TX/RX
- Programmable Interrupt Controller:
- Two internally cascaded 8259a interrupt controllers
- Nine external interrupt lines, including NMI
- Seven internal interrupts generated by peripherals
- Refresh Control Unit
- Strictly synchronous design with no internal tri-states
80186EC IP Core C80186EC 80186EC-Compliant Chip Replacement 16-bit Microcontroller Core
A semiconductor IP core that implements a pin-compatible replacement for the Intel® 80C186EC chip.
This 80186EC ISA compliant 16-bit microcontroller is a single-chip, high-performance design that executes the widely-known instruction set of Intel 80c86 or 80c186 devices. It has an extended peripheral set: three timers, two serial units, a watchdog timer, two universal interrupt controllers (8259a) and four DMA channels.
Compatibility with the original chip was ensured using hardware modeler-based reverse engineering. Software written for the original chip should execute on the C80186EC with little or no additional effort. A set of flexible outputs makes it easy to ensure pin-to-pin compatibility using current ASIC, Structured ASIC, or FPGA fabrication technologies, making obsolete part replacement straightforward and cost-effective for either low- or high-volume applications.
The microcode-free core design is strictly synchronous, with positive-edge clocking, no internal tri-states, and a synchronous reset; therefore scan insertion is straightforward.
See representative implementation results (each in a new pop-up window):
The C80186EC is designed for obsolete parts replacement, but can also serve well in embedded systems or as a new controller (because it requires little extra support from a chipset). Suitable 16-bit applications include high-speed control systems, microcomputer systems, automotive controls, and audio and video controls.
The 80186EC architecture suits low-power applications, such as this portable photo viewer. Images can be acquired from the USB and Firewire devices, and displayed on an LCD screen using the VGA Controller. NAND Flash memory stores the application firmware and its upgrades, while DRAM facilitates data exchange between system components. A C80187 numeric coprocessor improves system performance by accelerating floating-point calculations inside the CPU.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The C80186EC core’s instruction set functionality as well as the peripherals set were verified by means of a proprietary Personal Hardware Modeler. The same instructions and test scenarios were put as stimulus to a hardware model that contained the original Intel 80c186ec chip and the results of the operations were compared with the core’s simulation output. Subsequently, pin-to-pin compatibility was achieved.
The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
- Example CHIP80186EC module
- This chip level design uses the C80186EC IP core and illustrates how to build the module that is the pin replacement of the 80c(l)186ec device
- Sophisticated HDL Testbench
- Simulation script, vectors, expected results, and comparison utility
- Synthesis (soft) or place and route (firm) script
- Comprehensive user documentation, including detailed specifications and a system integration guide