- Control Unit
- 16-bit two levels instruction decoder
- Three levels instruction queue
- 55 instructions and 14 address modes
- Supervisor and User mode
- Independent stack for both modes
- Users registers
- Eight 32-bit data & address registers
- 16-bit status register
- Data format
- Integer 8, 16 or 32-bit
- BCD packet
- Bit
- Memory interface
- Independent data and address buses
- Asynchronous bus control
- 4 GB-address space
- 31-bit address bus (optional 32-bit)
- 8-address spaces (used 5)
- 16-bit data bus
- Interrupt Controller
- Seven Priority Levels
- Unlimited interrupt sources
- Manual or auto-vectored interrupt modes
- Arithmetic-Logic Unit
- 8, 16, 32-bit arithmetic and logic operations
- Boolean manipulations
- 16 x 16-bit multiplication (sign or unsigned)
- 32 / 16-bit division (sign or unsigned)
- M6800 peripherals family synchronous interface
- Two or Three wire bus arbitration interface
- Operation execution is the same for data or address registers
- No different for operation on data or address registers
- EASE debugging environment
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
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EASE Debugging Support for CAST Processor Cores
The TASKING 68K/ColdFire
Software Development Toolset supports this core
Related Information
Validated for Precision™ FPGA Synthesis
News Releases
- 03/27/00, CAST Unveils New Cores at DATE 2000
CAST Articles
Chip Replacement with IP and FPGAs: 68000 Processor Example
Other Resources
History at Wikipedia
Date yields testimonials and processor cores at EEDesign.com
Customer Application
Printer supplier for the pharmaceutical industry HAPA used the C68000 Core to develop a new replacement board design (bottom photo) that is dramatically more compact and less expensive to produce than the original (top photo).
68000 IP Core C68000 16/32-bit Microprocessor Core
The C68000 is core of a powerful 16/32-bit microprocessor and is derived from the Motorola MC68000 microprocessor. The C68000 is a fully functional 32-bit internal and 16-bit external equivalent for the MC68000. The C68000 serves interrupts and exceptions, and provides an interface for M6800 family peripherals.
The C68000 is the microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous without internal tri-states and with a synchronous reset. Scan insertion is straightforward.
See representative implementation results (each in a new pop-up window):
Applications
The C68000 core can be used for a variety of applications including:
- Microcomputer systems
- Embedded microcontroller systems
- Data computation and transfer
- High speed control systems
- Professional audio and video
Block Diagram
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements. All subcomponents were functionally verified with an HDL testbench using their individual test suites. The CPU and ALU have been verified against a proprietary hardware modeler and behavioral models. The peripherals have also been verified in their own testbenches, based on either hardware or behavioral models.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Vectors for testing the core
- Constraint file
- Instantiation templates
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
This core is sourced from the IP experts at Evatronix SA.
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