CAST C68000-AHB Core — XILINX FPGA Results

Xilinx results with the implementation constrained for clock speed including OCDS.

Xilinx Technology Area (slices) BRAM Hclk uP clock ISE Version

Spartan-3E
XC3S1200E-5

 3467 - 101 MHz 50 MHz 12.2i
Spartan-6
XC6SLX25-3		 1636 5 125 MHz 62 MHz 12.2i
Virtex-5
XC5VLX50-3		 4323 - 250 MHz 125 MHz 12.2i
Virtex-6
XC6SLX75T-3		 1456 5 251 MHz 125 MHz 12.2i

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