The following are sample ASIC results obtained using synthesis with no layout process considered, with only the CPU clock constrained as shown below.
| Device | Area |
Speed |
|
clk(MHz) |
hclk(MHz) |
||
| UMC 0.13 | 23,459 gates |
133 |
133 |
| UMC 0.18 | 24,214 gates |
150 |
150 |