Implementation optimization set to balanced.
| Altera Devices | Area | Speed | |
| clk(MHz) | hclk(MHz) | ||
Cyclone |
5822 LCs +4M4Ks |
59 | 262 |
| Cyclone II EP2C8F256C6 |
5564 LCs +4 M4Ks |
62 | 250 |
| Stratix EP1S10F484C5 |
5637 LCs +5 M4Ks |
61 | 286 |
| Stratix II EP2S15F484C3 |
4053 ALUT +5 M4Ks |
98 | 402 |