MOS Technology IP Core C65C0265C02-Compatible Microprocessor Core

This 65C02 IP core implements a fast, 8-bit microprocessor that executes the same instruction set as the 65C02 microprocessor. The 65C02 is an upgraded version of the popular MOS Technology 6502 8-bit CPU, and was used in many successful products such as the Apple IIc home computer.

The core provides software and hardware interrupts for interfacing external devices. With sixteen addressing modes—including indirect index and zero page—the C65C02 is able to address up to 64KB of external memory with two-byte-long instructions.

The 8-bit arithmetic logic unit can operate on signed and unsigned binary numbers as well as binary-coded decimal numbers.

The C65C02 core offer two instruction to save power by (STP) halt processor and (WAI) wait for interrupt instruction.

The popularity of the 6502 architecture means a significant amount of industry-certified software is ready to use with this core. The core also enables modification of the original instruction set to better suit new systems and applications.

See representative implementation results (each in a new pop-up window):

Applications

The C65C02 core is a suitable chip replacement for extending the lifetime of existing systems, affording independence from any particular chip manufacturer. The core can also serve as an effective embedded processor for many new applications in ASIC or FPGA SoCs, including:

• 8-bit data processing applications
• Low-power consumption applications
• High-speed control systems

Block Diagram

 

 

Example Application

 

This figure above shows typical application of the C65C02 core.

The example application uses the Commodore C64 home computer board with the C65C02 IP core. The main board is equipped with:

• VIC – Video Interface Chip
• SID – Sound Interface Device
• CIA – Complex Interface Adapter

Support

The core, as delivered, is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, beginning with the first interaction. Additional maintenance and support options are available.

Verification

Functionality of the C65C02 was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original 65C02 chip, and the results compared with the core simulation outputs.

Deliverables

The core includes everything required for successful implementation:

• HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
• An example C65C02 application
• Sophisticated HDL Testbench including external RAM, clock generator, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including detailed specifications and a system integration guide

 

This core is sourced from the IP experts at Evatronix SA.