Z80 IP Core C6502 MOS Technology® 6502-compatible Microprocessor Core

This 6502 IP core implements a fast, 8-bit microprocessor that executes the same instruction set as the MOS Technology 6502. It also conforms to the popular 6510 and 6502C variations of the 6502.

The core provides software and hardware interrupts for interfacing external devices. With thirteen addressing modes—including indirect-index and zero-page modes—the C6502 is able to address up to 64KB of external memory with two byte-long instructions. The 8-bit arithmetic-logic unit can operate on signed and unsigned binary numbers as well as binary-coded decimal numbers.

The popularity of the 6502 architecture means a significant amount of industry-certified software is ready to use with this core. The core also enables modification of the original instruction set to better suit new systems and applications.

See representative implementation results (each in a new pop-up window):

Applications

The C6502 core is a suitable chip replacement for extending the lifetime of existing systems, affording independence from any particular chip manufacturer. The core can also serve as an effective embedded processor for many new applications in ASIC or FPGA SoCs, including:

• 8-bit data processing applications,
• Low-power consumption applications, and
• High-speed control systems

Block Diagram

Example Application

This figure shows a typical application of the C6502 core.

The core is implemented with internal I/O port and tri-state buffers as in the elated C6510. The example application uses Commodore C64 home computer board with the C6502 IP core. The main board is equipped with:

• VIC – Video Interface Chip
• SID – Sound Interface Device
• CIA – Complex Interface Adapter

Support

The core, as delivered, is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, beginning with the first interaction. Additional maintenance and support options are available.

Verification

The C6502 functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original 6502 MOS Technology chip, and the results compared with the core simulation outputs. The core has been developed according to requirements of Reuse Methodology Manual and it has achieved high score of VSIA Quality IP Assessment. The C6502 has been verified through extensive functional simulation and it has achieved high Code Coverage simulation results.

Deliverables

The core includes everything required for successful implementation:

• HDL source code (soft core) or a post-synthesis EDIF netlist (firm core)
• An example C6502 application
• Sophisticated HDL Testbench
• Simulation script, vectors, expected results, and comparison utility
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including detailed specifications and a system integration guide

This core is sourced from the IP experts at Evatronix SA.