Results optimized for speed including a clock divider, FIFIO memory & tri-state buffers with the following parameters: bus width: 134, mantisa width: 70, BIU data bus width: 32, exponent width: 16, address width: 6.
| Altera Device | LEs/ ALUTs |
Memory | Memory Bits | DSP | I/Os | Fmax (MHz) |
Quartus |
| Cyclone-II EP2C35-6 |
17,875 | 12 M4Ks | 41,216 | - | 31 | 58 | 7.0 |
| Cyclone-III EP3C40-6 |
17,561 | 8 M9Ks | 41,216 | - | 31 | 69 | 7.0 |
| Stratix-II EP2S30-3 |
11,155 | 3 M512s / 11 M4Ks |
41,856 | - | 31 | 87 | 7.0 |
| Stratix-III EP3SE50-2 |
11,598 | 9 M9Ks | 41,728 | - | 31 | 115 | 7.0 |