The following are sample Altera results with the pixel clock fixed at 27 MHz, and areas reported for a FIFO with 32-bit-wise data, depth – 9.
| Altera Devices | Area | Speed |
| Cyclone EP1C4F324C6 |
2035 ALUTs 4 M4Ks |
70 MHz |
| Cyclone 2 EP2C20F484C6 |
2052 ALUTs 4 M4Ks |
106 MHz |
| Stratix EP1S20F484C5 |
2030 ALUTs 4 M4Ks |
84 MHz |
| Stratix 2 EP2S15F484C3 |
1700 ALUTs 4 M4Ks |
110 MHz |