SCR Core — XILINX FPGA Results

The SCR can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results for the APB version, optimized for area and using a 2 x 8 byte FIFO. Please contact CAST to get characterization data for your target configuration and technology.

Xilinx Devices Area
BRAM Fmax
(MHz)
Spartan-6
6SLX25-2
246 Slices - 84
Virtex-4
4VLX25-10
436 Slices - 165
Virtex-5
5VLX30-1
192 Slices - 144
Virtex-6
6VLX75T-1
172 Slices - 180
Artix-7
7A15T-1

240 Slices

650 LUts
- 161
Kintex-7
7K70T-1

220 Slices

657 LUTs
- 271

Kintex UltraScale

KU025-1
131 CLBs
674 LUTs
- 339

Kintex UltraScale+
KUP03-1

119 CLBs
677 LUTs

- 488

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