SCR Core — Lattice Implementation Results

The SCR can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results for the APB version, optimized for area and using a 2 x 8 byte FIFO. Please contact CAST to get characterization data for your target configuration and technology.

Lattice Devices LUT-4s Registers PFUs SysMEM
EBRs
External I/Os Speed
(fmax, MHz)
ispXPGA
LFX200C-4
705 427 248 54 60
ORCA-4E
OR4E02-3
757 396 131 54 71

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