SCR Core ASIC Implementation Results

The SCR can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results for the APB version. Please contact CAST to get characterization data for your target configuration and technology.

ASIC Technology

Cell Area NAND2 Area

Approx. Area


TSMC 0.18µm process

80,764 9.9792

8,093 gates

260 MHz

TSMC 0.13µm process
37,921 5.0922

7,447 gates

423 MHz

TSMC 90 nmprocess 19,703 2.8224 6,980 gates 775 MHz
TSMC 65 nm process 12,878 1.6 8,049 gates 1040 MHz

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