SCR Core — Intel Implementation Results

The SCR can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results for the APB version, optimized for area and using a 2 x 8 byte FIFO. Please contact CAST to get characterization data for your target configuration and technology.

Intel Devices LEs
Memory I/Os Fmax
(MHz)
Cyclone
EP1C6-7
765 2 M4Ks 54 140
Cyclone-II
EP2C8-8
744 2 M4Ks 54 122
Stratix
EP1S10-7
765 2 M512s 54 131
Stratix-II
EP2S15-4
692 2 M512s 54 203

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