SCR Core — Microsemi Implementation Results

The SCR can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample Microsemi results for the APB version, optimized for area and using a 2 x 16 byte FIFO. Please contact CAST to get characterization data for your target configuration and technology.

Microsemi Devices Cells Ram
Blocks
I/Os Fmax
(MHz)
Sequ (R) Comb (C)
Axcelerator
AX125-3
412 1030 2 54 47
ProASIC
A500K050-STD
413 1679 2 54 38

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