Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.
   Stack

IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • Supports the ISO/IEC 7816-3:2006 and EMV2000 4.2 specifications
  • Performs functions needed for complete smart card sessions, including:
    • Card activation and deactivation
    • Cold/warm reset
    • Answer to Reset (ATR) response reception
    • Data transfers to and from the card
  • Extensive interrupt support system
  • Adjustable clock rate and bit (baud) rate
  • Configurable automatic byte repetition
  • Handles commonly used communication protocols:
    • T=0 for asynchronous half-duplex character transmission, and
    • T=1 for asynchronous half-duplex block transmission
  • Automatic convention detection
  • Automatic voltage class selection
  • Adjustable FIFOs for Receive and Transmit buffers (up to 32k characters) with threshold
  • Configurable timing functions:
    • Smart card activation time
    • Guard time
    • Timeout timers
  • Supports synchronous and any other non-ISO 7816 and non-EMV’96 or EMV2000 cards
  • Standard system interface wrapper architecture for easy integration with host systems
  • Fully-synchronous design suitable for scan-based testing
  • Available in synthesizable HDL source code (versions for FPGAs also available)

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Articles

Smart Card Tutorial by Dr. David B Everett, from the Smart Card News site

Info and links to numerous additional resources in the alt.technology.smartcards FAQ

Info on Smart Cards and a 7816 summary at Didya.com

Purchase the ISO/IEC 7816-3:1997 standard

SCR Smart Card Reader Controller Core

Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces.

The SCR supports the ISO/IEC 7816-3:2006 and EMV2000 4.2 specifications, which define the electrical signals and transmission protocols for smart cards (also known as integrated circuit cards). It acts as a communication controller, passing data to and from the host system and the smart card. It is fully-featured, and can activate and deactivate cards, perform cold/warm resets, handle ATR response reception, and execute other essential functions.

The SCR consists of the core smart card reader logic with a wrapper for the desired system interface. (AMBA APB and Wishbone interfaces are available; support for other bus interfaces is optional.)

The core is fully synchronous for easier testing and is designed for efficient ASIC or FPGA implementation. It requires, for example, just 6,500 ASIC gates and operates at 300 MHz (TSMC 0.13).

This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):

ASIC numbers Microsemi numbersAltera numbersLattice numbersXilinx numbers

Applications

Smart cards embed a computer chip in a credit-card sized plastic card, and are gaining global popularity for a variety of applications, including:

 

Block Diagram

SCR Block Diagram

 

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

 

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