SCR

Smart Card Reader Controller

The SCR manages the interactions between an inserted smart card and the host system. It handles all timing issues, and safely transfers data from and to the card.

As shown in the block diagram, the core consists of a main SCR core block which performs according to the 7816 specification, and a wrapper that interfaces the SCR functions to a host system with APB.

SCR Top Level Entity

The wrapper that connects the SCR core to the AMBA APB. It converts the APB signals and makes them useful to the core.

Smart Card Reader Core

Contains five blocks that implement the SCR, and communicates with the host system through the APB wrapper.

Configuration Registers

Store values that provide control over all SCR functions.

Controller with UART

The main functional block, controlling the received and transmitted characters and performing card activation and deactivation, and cold and warm reset.
Includes a UART (Universal Asynchronous Receiver Trans-mitter) that converts the data from parallel to serial for transmitting from the SCR to a Smart Card and from serial to parallel for transmitting from a Smart Card to the SCR. The UART also performs the guard time, parity checking, and character repeating functions.

Receive FIFO

Stores the data received from the smart card until it is read out by the host system.

Transmit FIFO

Stores the data to be transmitted to the smart card.

Clock Generator

Generates the Smart Card Clock and the Baud Clock Im-pulse signals, used in timing the SCR.

The core has been verified through extensive simulation, synthesis, and rigorous code coverage measurements. It has been embedded in numerous shipping customer products, and is proven in both ASIC and FPGA technologies

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core includes everything required for successful implementation:

• HDL RTL source code or FPGA netlist
• Sophisticated, self-checking HDL Testbench including everything necessary to test the core
• Sample driver in C code
• Scripts for simulation and synthesis 
• Comprehensive user documentation, including detailed specifications and design integration guidelines

The SCR can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results for the APB version. Please contact CAST to get characterization data for your target configuration and technology.

The SCR can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results for the APB version, optimized for area and using two 32x8  FIFOs. Please contact CAST to get characterization data for your target configuration and technology.

The SCR can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results for the APB version, optimized for area and using a 2 x 8 byte FIFO. Please contact CAST to get characterization data for your target configuration and technology.

The SCR can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results for the APB version, optimized for area and using a 2 x 8 byte FIFO. Please contact CAST to get characterization data for your target configuration and technology.

The SCR can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample Microsemi results for the APB version, optimized for area and using a 2 x 16 byte FIFO. Please contact CAST to get characterization data for your target configuration and technology.

The SCR core is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced version is certified as ISO-26262 ASIL-B Ready.