Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Embedded Processors
BA22 Real-Time Embedded
BA22 Deeply Embedded
BA21 Low Power

8051 Microcontrollers
XC3: super-fast, advanced
XC2: fast, mature

Peripheral Platforms
& AMBA Infrastructure

BA2x AHB Platform
BA2x AXI Platform

 

GPUs & Peripherals
See Graphics &
  Peripherals Cores >

These video and image compression cores and subsystems help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
Encoder
J2K Platform

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Complement or replace system processors with GPUs and easily integrate memories, peripherals, and hardware networking stacks into SoCs.

NOR Flash Controllers
Serial/SPI NOR Flash
Parallel NOR Flash

Device Controllers
smart card reader

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

AMBA Infrastructure
AMBA Infrastructure Cores
AHB 32-bit DMA


Interconnect Peripherals

See Interconnect Cores >

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

DisplayPort
Transmitter
•  Receiver

Ethernet MAC
•  1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
Hardware RTP Stack for H.264

PCI — Target
32-bit
32-bit multi
64-bit
PCI — Master
32-bit
32-bit multi
64-bit
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

PCI Express
Family Overview
x1/x4
x8
application interface


Data Link Controllers

• SDLC
• HDLC

These encryption cores make it easy to build security into a variety of systems.

DES
DES single
DES triple

  • Supports the ISO/IEC 7816-3:1997(E) and EMV’2000 4.0 specifications
  • Performs functions needed for complete smart card sessions, including:
    • Card activation and deactivation
    • Cold/warm reset
    • Answer to Reset (ATR) response reception
    • Data transfers to and from the card
  • Extensive interrupt support system
  • Adjustable clock rate and bit (baud) rate
  • Configurable automatic byte repetition
  • Handles commonly used communication protocols:
    • T=0 for asynchronous half-duplex character transmission, and
    • T=1 for asynchronous half-duplex block transmission
  • Automatic convention detection
  • Automatic voltage class selection
  • Adjustable FIFOs for Receive and Transmit buffers (up to 32k characters) with threshold
  • Configurable timing functions:
    • Smart card activation time
    • Guard time
    • Timeout timers
  • Supports synchronous and any other non-ISO 7816 and non-EMV’96 or EMV2000 cards
  • Standard system interface wrapper architecture for easy integration with host systems
  • Fully-synchronous design suitable for scan-based testing
  • Available in synthesizable HDL source code (versions for FPGAs also available)

Contact Sales
Call or click.
+1 800.391.8300

PDF Datasheets

ASIC
Microsemi, Altera , Lattice, Xilinx

Related Products

Related Information

Validated for Mentor Graphics Presicision FPGA SynthesisValidated for Precision™ FPGA Synthesis

 

News Releases

Articles

Smart Card Tutorial by Dr. David B Everett, from the Smart Card News site

Info and links to numerous additional resources in the alt.technology.smartcards FAQ

Info on Smart Cards and a 7816 summary at Didya.com

Purchase the ISO/IEC 7816-3:1997 standard

Smart Card IP Core SCR Smart Card Reader Controller Core

Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces.

The SCR supports the ISO/IEC 7816-3:1997(E) and EMV2000 4.0 specifications, which define the electrical signals and transmission protocols for smart cards (also known as integrated circuit cards). It acts as a communication controller, passing data to and from the host system and the smart card. It is fully-featured, and can activate and deactivate cards, perform cold/warm resets, handle ATR response reception, and execute other essential functions.

The SCR consists of the core smart card reader logic with a wrapper for the desired system interface. (AMBA APB and Wishbone interfaces are available; support for other bus interfaces is optional.)

The core is fully synchronous for easier testing and is designed for efficient ASIC or FPGA implementation. It requires, for example, just 6,500 ASIC gates and operates at 300 MHz (TSMC 0.13).

See representative implementation results (each in a new pop-up window):

ASIC numbers Microsemi numbersAltera numbersLattice numbersXilinx numbers

Applications

Smart cards embed a computer chip in a credit-card sized plastic card, and are gaining global popularity for a variety of applications, including:

 

Block Diagram

SCR Block Diagram

 

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation: