HD Video IP Core DISPLAY-CTRL Configurable High-Resolution Video Display Controller Core
The core accepts two different standard input formats — 15-bit (5:5:5) and 24-bit (8:8:8) RGB — and produces 24-bit RGB pixel data. It also generates all of the required horizontal and vertical timing periods: horizontal and vertical front porch, back porch and sync intervals. Video aspect ratios and monitor frequencies are configurable, and various display functions are provided.
The core passes 24-bit RGB to standard analog/digital video converters such as Analog Devices’ ADV7120 CMOS, 80MHz, Triple 8-Bit Video DAC (ADV®). The DAC then generates output signals compatible with RS-343A/RS-170 standards.
Test and power save modes are built into the core. The design is strictly synchronous with positive-edge clocking, no internal tri-states and asynchronous reset; therefore scan insertion is straightforward. ASIC implementation results show it to require about 14,000 gates in a TSCM 90nm process.
- Generates color and control data for standard displays in the following
- QVGA 320 x 240 85Hz
- VGA 640 x 480 85Hz
- SVGA 800 x 600 85Hz
- XGA 1024 x 768 85Hz
- SXGA 1280 x 1024 85Hz
- HD 720 1280 x 720 60Hz
- UXGA 1600 x 1200 60Hz
- HD 1080 1920 x 1080 60Hz
- WUXGA 1920 x 1200 60Hz
- Works in conjunction with external video DAC such as Analog Devices’
- Accepts two standard video data formats:
- 24-bit RBG (8:8:8)
- 15-bit RBG (5:5:5)
- Output interface
- 8:8:8 24-bit RGB video
- HSYNC and VSYNC signals or one composite
- Blanking (Data Enable) signal
- Display functions with hardware support:
- Scroll (in horizontal and vertical directions)
- Sub-screen display (any position)
- Horizontal flip screen
- Fully configurable monitor frequencies and aspect ratios
- Progressive scanning mode
- 32-bit data path
- Configurable internal FIFO
- Integrated Test mode: core generates color bar without any AHB bus transactions
- Internal, event-stimulated, interrupt request generation with masking capability
- Dedicated unidirectional DMA controller with burst transaction support
- Built-in Power Save mode
- Integrated with AMBA™ bus:
- AMBA™ AHB slave unit interfaces with host controller
- AMBA™ AHB master unit interfaces with host memory
The core is designed to work with a video data processor in a variety
of video display systems, including:
- Portable video systems
- Digital cameras with video output
- Advanced mobile phones with video capabilities
The core combines a flexible data generation module with additional elements necessary to communicate with its host system, accept and convert different forms of video data, and store that data for processing and output.
Unidirectional DMA controller with an AHB Master Interface. It is implemented to take image data from the AHB data bus. The AHB Master Interface is compatible with the ARM® AMBA™ Advanced High-speed Bus (AHB) interface standard specification version 2.0. It operates as a master device for data transfers, and only read transfers can be initiated. It supports a 32-bit width data bus and a 32-bit width address bus. The AHB Master can initiate only one of the following transfer types: SINGLE, INCR, or INCR16.
Bidirectional AHB Slave Interface for the CONTROL block. The AHB Slave Interface is compatible with the ARM® AMBA™ Advanced High-speed Bus (AHB) interface standard specification version 2.0. It supports a 32-bit width data bus and a 32-bit width address bus. The AHB Slave supports only SINGLE transfers.
RGB format converter. Converts input RGB15 format to output RGB24 format and stores into the FIFO.
Pixel data output and synchronization module. The RGB module takes data from the FIFO and outputs this data with horizontal and vertical synchronization signals (HSYNC and VSYNC), as well as the video blanking signal (Data Enable). Additionally it generates data in test-mode without any AHB bus activity.
Software reset generation and synchronization module.
Write FIFO CTRL & Read FIFO CTRL
FIFO component implemented in a Dual Port RAM. It is designed to buffer pixel data between the CONV and RGB units and works in two clock domains. The size of the FIFO buffer is parameterized. There are two controllers: WRITE FIFO CTRL for writing data from CONV to FIFO and READ FIFO CTRL for reading data from FIFO to RGB.
The core was designed to make the integration of a high-resolution display controller into an application-specific integrated circuit (ASIC) or a system-on-a-chip (SoC) design easy to accomplish
This application enables transmission of data from the host memory to an LCD monitor, or a CRT monitor, or a TFT panel. The CPU controls the configuration of the core and process interrupt requests using an AMBA™ AHB Slave bus. Data from the host memory are sent to the DISPLAY-CTRL through an AMBA™ AHB Master interface. The DISPLAY-CTRL outputs data in RGB24 format. Examples of supported Video DAC devices are:
- ADV7120 – Analog Devices, 80MHz Triple 8-Bit Video DAC
- CH7301C – Chrontel, DVI Transmitter up to 165M pixels/second
- AD9889B – Analog Devices, 165MHz HDMI/DVI Transmitter
- ST7787 – Sitronix, 262K Color Single-Chip TFT Controller/Driver
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core’s functionality was verified by processing bitmap pictures. These were converted by a C program into stimuli and reference files. The stimuli files were applied to core inputs, and the reference files compared with the core simulation outputs.
Various resolutions of the core were verified in an AHB bus based system implemented in hardware. Higher resolutions use the Chrontel CH7301C DVI Transmitter up to 165 Mpixels/second.
The DISPLAY-CTRL has also been verified through extensive functional simulation and it has achieved high Code Coverage results. A demo system has been implemented.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated self-checking HDL Testbench including:
- An example system design
- External Dual Port TAM
- Behavioral model of an external Video DAC
- Example AMBA™ bus systems
- Clock generator
- Simulation scripts, vectors, and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including a detailed specification, system integration guide and a verification specification