CAST DISPLAY-CTRL Core — XILINX FPGA Results

Xilinx results with a FIFO size of 512x64 bits implemented.

Xilinx Devices Slices BRAM I/Os Fmax
(MHz)		 ISE
Spartan-3E
XC3S1600E-5		 1009 2 298 95
 12.1i
Spartan-6
XC6SLX75-3		 452 2 298 125
 12.1i
Virtex-5
 XC5VLX50-3		 559 1 298 204
 12.1i
Virtex-6
XC6SLX75T-3		 438 2 298 270
 12.1i

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