Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream

Octal SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Data Link Controllers
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES, programmable
Key Expander

DES single
DES triple

Hash Functions
SHA-3 (Keccak)

  • AHB Master/Slave DMA Controller
  • Four DMA Channels
  • Modes:
    • Memory to Memory
    • Memory to Peripheral
    • Peripheral to Memory
    • Peripheral to Peripheral
  • Source and destination address descriptors
  • Single word and burst transfer requests
  • Programmable burst size
  • Current address status
  • Incrementing, wrapping, and non-incrementing addressing
  • Linked list support
  • Transfer complete interrupt
  • Low gate count, e.g., under 44,000 gates for 90nm ASIC
  • Scatter-gather support allows DMA to merge multiple data sources into contiguous space
  • Supports both hardware initiated transfers and software initiated transfers
  • Supports 8-, 16-, or 32-bit wide transfers
  • Supports burst transfer to maximize data bandwidth
  • Bus Interface designed for high-speed access to any AHB slave device
  • Handles wait-state insertion by any AHB slave device
  • Supports all responses from an AHB slave device: OK, SPLIT, RETRY, ERROR

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Related Cores

  • C8237 Programmable DMA Controller
  • C82380 32-bit DMA Controller
  • DMA Direct Memory Access Controller
  • AXI MultiLayer Fabric
  • AXI to AHB Lite Bridge
  • AXI to APB Bridge
  • AXI External Bus Interface (Parallel Flash/SRAM)
  • AHB to APB Bridge
  • AXI External Bus Interface (Parallel Flash/SRAM)
  • AHB MultiMatrix Fabric
  • AHB Arbiter
  • AHB Channel with Decoder and Data-Mux
  • AHB Lite to AHB Bridge
  • AHB Single Channel DMA
  • AHB Quad Channel DMA
  • APB Channel with Decoder and Data-Mux
  • AHB Interrupt Controller
  • AHB TFT LCD Controller
  • AHB Quad Serial Peripheral Interface Master/Slave
  • APB General Purpose IO
  • APB Pulse Width Modulator
  • APB Real Time Clock
  • APB Counter-Timer
  • APB 16450/16550 Compatible UART
  • APB I2C Bus Controller Master
  • APB I2C Bus Controller Slave
  • APB Watchdog Timer


  • AHB-LP – AHB Low Power Subsystem
  • AHB-PLP – AHB Performance / Low Power Subsystem
  • AXI-CP – AXI Custom Subsystem

DMA4 Multi-Channel Direct Memory Access Controller IP Core

This DMA4 IP core implements a configurable, multi-channel, direct memory access controller for the 32-bit wide AHB bus. It conforms to the Advanced Microcontroller Bus Architecture 2.0 (AMBA) specification.

The DMA4 controller contains useful features such as incrementing and non-incrementing addressing, linked list operation, and interrupt control to alert the processor to the DMA’s status.

Non-incrementing addressing is useful for transferring data to and from peripherals with FIFOs or a single data port. Incrementing addressing is useful for transferring data to and from memories or peripherals containing memory. Linked list support is useful for non-contiguous memory transfer operations.

The DMA4 controller acts as a bus master device that controls data block transfers from a source memory or peripheral to a destination memory or peripheral,. The DMA Channel Arbiter determines which DMA Channel has access to the external AHB Master Bus. A round-robin algorithm is implemented in which each active channel has equal priority.

See representative implementation results ( in a new pop-up window):

ASIC numbers


The DMA4 controller is suitable for a variety of applications requiring data transfers without the use of a processor, such as:

Block Diagram

DMA4 Block Diagram


The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available; contact CAST Sales.


The core has been verified through extensive simulation and system level prototyping using ARM based systems. It has also been successfully embedded in several products.


The core is available in ASIC (synthesizable Verilog) or FPGA (netlist) forms, and includes everything required for successful implementation:



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