Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Adds single or multilevel cache memory to originally cache-less deeply embedded processors, DSPs, or ASIPs. Improves access time and reduces bandwidth to DRAM, Flash or EEPROM memories; enables XIP without typical power or performance penalties.

Cache Parameters

  • Four-way set associative cache
  • Least Recently Used (LRU) replacement policy
  • Synthesis-time configurable:
    • number of cache lines
    • number of words per line
  • 32-bit words
  • Invalidates cache contents if a write access occurs

Easy Integration & Implementation

  • Works with any processor with a 32-bit AHB bus
    • 32-bit AHB slave interface towards the processor
    • 32-bit AHB master interface towards the memory system
  • Uses four single-ported SRAMs: no special type of RAM is required
  • Scan-ready design
  • Supports clock gating

Deliverables

  • Verilog RTL source code or targeted FPGA netlist
  • Verification environment using System Verilog
  • Assertions and Bus Functional Models
  • Sample synthesis and simulation scripts
  • User Documentation

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News Releases

CACHE-CTRL AHB Cache Controller Core

The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32-bit master AHB interface to the memory subsystem.

The cache controller core supports a four-way associative cache memory, and implements a Least Recently Used (LRU) replacement policy. The number of cache lines and the cache line width are configurable at synthesis time. The core only caches read accesses and invalidates the cached data if a write access to a cached memory location occurs. 

Mapping the cache controller to any technology is straightforward, as the core does not require any special type of SRAM modules, only using standard, single-ported SRAMs. Furthermore, the design is scan-ready as it uses only rising-edge triggered flip-flops and contains no internal tri-states. Integration of the core is trouble-free, as the core uses standard 32-bit AHB interfaces, and supports clock gating.

The CACHE-CTRL core has been robustly verified and is silicon-proven.  

Applications

The CACHE-CTRL can be used to add single or multilevel cache memory to cache-less deeply embedded processors, DSPs, or ASIPs. This can decrease the read access time and bandwidth to a relatively slow or energy consuming memory resource like flash, EEPROM, or DRAM devices. For example it allows economical processors like the BA20, BA21, or BA22-DE to run code directly from an off-chip NOR-flash (XIP) while minimizing the typical performance and/or power penalties of off-chip access.

Implementation Results

CACHE-CTRL reference designs have been evaluated in a variety of technologies. When configured with eight words per line and 256 lines per set (1024 lines in total) the core synthesizes to about 9,000 equivalent NAND2 gates. It can run over 1GHz when mapped in a typical 28nm technology. Please contact CAST to get resource utilization and performance information for your preferred core configuration and ASIC technology.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Block Diagram

CACHE-CTRL AHB Cache Controller Core Block Diagram

 

tw    fbk    li    li    li
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