PCIe Endpoint IP Core PCIEXPAIFApplication Interface Core for Altera and Xilinx FPGA PCIe Hard IP

On this page: Description | Implementation Results | Features | Block Diagram | Functional Description | Support | Verification | Deliverables | Example Application

Implements a PCI Express application-level interface that simplifies the integration of the hard macro PCIe controllers available from Altera and Xilinx.

The core integrates a completer controller and DMA controller with up to eight DMA channels. The functionality of the DMA controller can be extended using the Scatter-Gather controller. The Application Interface (AIF) provided by this core is more than a just a DMA core, as it also capable of encoding and decoding for Transaction Layer Packets (TLP). Relieving the SoC designer from the complexity of TLP handling, this core makes integrating PCI Express in a system significantly easier than using other DMA cores for the PCIe Hard IP block.

The PCIEXPAIF megafunction for Altera is compatible with Cyclone IV GX, Arria II GX, Stratix IV GX, and Stratix V GX devices.

The PCIEXPAIF core for Xilinx is compatible with Virtex-5, Virtex-6 and Spartan-6 devices. Supported SoC busses are 32bits and 64bits versions of Wishbone, AMBA™ AHB, AXI and AXI4.

See representative implementation results (each in a new pop-up window):

Features

• TLP Encoding/Decoding and Completion Controller for easier system integration
• Flexible DMA
• Configurable FIFO sizes
• Up to eight independent DMA channels
• Optional Scatter-Gather functionality
• Control registers accessible from SoC bus and PCIe bus side
• Interrupt support
• Provides interface to popular system buses:
• Wishbone bus specification compliant
• AMBA AHB
• AMBA AXI
• AMBA AXI4
• Provides interface to popular system buses:
• Wishbone bus specification compliant
• AMBA AHB
• AMBA AXI
• AMBA AXI4
• Altera version supports these devices:
• Cyclone IV G,
• Arria II GX,
• Stratix IV GX, and
• Stratix V GX
• Xilinx version supports these devices:
• Virtex-5
• Virtex-6
• Spartan-6

Block Diagram

 

Functional Description

The core is divided into following main modules:

Conversion module provides interface conversion between PCIe Hard IP block and native CPXP-AIF core.

TLP decoder decodes TLP packets received from the PCIe Hard IP block and provides appropriate data and parameters to the application interface subsystems processing received packet data.

TLP generator generates TLP packets using parameters and data provided by the application interface subsystems. TLP packets are then sent to the PCIe Hard IP block.

Completer responds to memory and I/O read or write requests.

DMA controller performs data transfers between local bus system and a memory located in the PCIe address space. The DMA controller implements up to 8 independent DMA channels.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation. It has also been verified in a prototyping FPGA board platform.

Deliverables

The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source or post-synthesis netlist
  
• Sophisticated HDL Testbench including models of interfaces, and the core
  
• Simulation scripts, vectors, expected results
  
• Place and route scripts
• Comprehensive user documentation

Example Application

On this page: Description | Implementation Results | Features | Block Diagram | Functional Description | Support | Verification | Deliverables | Example Application

Download PDF datasheets for more info: Altera | Xilinx