Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • TLP Encoding/Decoding and Completion Controller for easier system integration
  • Flexible DMA
    • Configurable FIFO sizes
    • Up to eight independent DMA channels
    • Optional Scatter-Gather functionality
  • Control registers accessible from SoC bus and PCIe bus side
  • Interrupt support
  • Provides interface to popular system buses:
    • Wishbone bus specification compliant
    • AMBA AHB
    • AMBA AXI
    • AMBA AXI4
  • Provides interface to popular system buses:
    • Wishbone bus specification compliant
    • AMBA AHB
    • AMBA AXI
    • AMBA AXI4
  • Altera version supports these devices:
    • Cyclone IV G,
    • Arria II GX,
    • Stratix IV GX, and
    • Stratix V GX
  • Xilinx version supports these devices:
    • Virtex-5
    • Virtex-6
    • Spartan-6

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

  • CPXP-EP PCI Express Endpoint Controller Core with SoC Bridge Extensions for AHB, AXI and Wishbone
  • CPXP-EPx8 PCI Express Endpoint Controller Core with SoC Bridge Extensions for AMBA™ AXI

Articles

Avoiding unexpected challenges in PCI Express core integration, April, 2006, Embedded Computing Design

PCIEXPAIFApplication Interface Core for Altera and Xilinx FPGA PCIe Hard IP

Implements a PCI Express application-level interface that simplifies the integration of the hard macro PCIe controllers available from Altera and Xilinx.

The core integrates a completer controller and DMA controller with up to eight DMA channels. The functionality of the DMA controller can be extended using the Scatter-Gather controller. The Application Interface (AIF) provided by this core is more than a just a DMA core, as it also capable of encoding and decoding for Transaction Layer Packets (TLP). Relieving the SoC designer from the complexity of TLP handling, this core makes integrating PCI Express in a system significantly easier than using other DMA cores for the PCIe Hard IP block.

The PCIEXPAIF megafunction for Altera is compatible with Cyclone IV GX, Arria II GX, Stratix IV GX, and Stratix V GX devices.

The PCIEXPAIF core for Xilinx is compatible with Virtex-5, Virtex-6 and Spartan-6 devices. Supported SoC busses are 32bits and 64bits versions of Wishbone, AMBA™ AHB, AXI and AXI4.

See representative implementation results (each in a new pop-up window):

PCIe core Altera numbers PCIe core Xilinx numbers

Block Diagram

PCIEXPAIF Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation. It has also been verified in a prototyping FPGA board platform.

Deliverables

The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation:

Example Application

pciexpaif application

 

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