Avoiding unexpected challenges in PCI Express core integration, April, 2006, Embedded Computing Design
- CAST Simplifies PCI Express FPGA Integration with Application-Level Interface Core
- CAST Offers PCI Express Model, Highlights APS 32-bit Processor Cores at DAC 2007
- CAST Selects Avery Design Systems for PCI Express Verification IP
- CAST Announces PCI Express Endpoint Controller IP Core
Download our DATE 06 slides: PCI Express Core Integration with the OCP Bus
PCI Express IP Cores
This page provides resources and helpful links for designers using PCI Express cores, as well as an introduction to CAST's line of IP cores for PCIe.
PCIe Simulation Model Download
Qualified designers can get our PCIe Core Backend Model for free. This package has everything you need to simulate a complete system using our Endpoint Controller core (in Verilog, for ModelSim). Run the included Test Cases and Design Example, or write your own system code, and learn more about PCI Express at the critical transaction packet level.
CAST PCI Express Cores
The CPXP-EP Endpoint Controller Core for PCI Express features an Application Interface module for easier integration with less knowlwdge of PCIe internal details.
The CPXP-EPx8 PCI Express Endpoint Controller Core with SoC Bridge Extensions for AMBA™ AXI Core implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It is available to act as a bridge to the standard AMBA™ AXI bus.
The PCIEXPAIF Application Interface Core for Altera and Xilinx FPGA PCIe Hard IP is designed to provide connection between the FPGA PCIe Hard IP block and SoC local bus. Supported SoC busses are Wishbone, AMBA™ AHB and AMBA™ AXI.